From: Hongtao Liu <crazylht@gmail.com>
To: Richard Biener <richard.guenther@gmail.com>
Cc: Jacob Lifshay <programmerjake@gmail.com>,
"H.J. Lu" <hjl.tools@gmail.com>,
GNU C Library <libc-alpha@sourceware.org>,
llvm-dev <llvm-dev@lists.llvm.org>,
GCC Patches <gcc-patches@gcc.gnu.org>,
IA32 System V Application Binary Interface
<ia32-abi@googlegroups.com>,
Joseph Myers <joseph@codesourcery.com>
Subject: Re: [llvm-dev] [PATCH] Add optional _Float16 support
Date: Fri, 2 Jul 2021 16:03:25 +0800 [thread overview]
Message-ID: <CAMZc-bw5kXMuMc1JnrROYWWL97uSYZbMaQ0u5VvyPWGmBm68_A@mail.gmail.com> (raw)
In-Reply-To: <CAFiYyc2-1Qpb=xas9hAk1KFcYGgEY8S+ENbBrcc_L-OrQvh83g@mail.gmail.com>
On Fri, Jul 2, 2021 at 3:46 PM Richard Biener via llvm-dev
<llvm-dev@lists.llvm.org> wrote:
>
> On Fri, Jul 2, 2021 at 1:34 AM Jacob Lifshay via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> > On Thu, Jul 1, 2021, 15:28 H.J. Lu via llvm-dev <llvm-dev@lists.llvm.org>
> > wrote:
> >
> > > On Thu, Jul 1, 2021 at 3:10 PM Joseph Myers <joseph@codesourcery.com>
> > > wrote:
> > > >
> > > > On Thu, 1 Jul 2021, H.J. Lu via Gcc-patches wrote:
> > > >
> > > > > 2. Return _Float16 and _Complex _Float16 values in %xmm0/%xmm1
> > > registers.
> > > >
> > > > That restricts use of _Float16 to processors with SSE. Is that what we
> > > > want in the ABI, or should _Float16 be available with base 32-bit x86
> > > > architecture features only, much like _Float128 and the decimal FP types
> > >
> > > Yes, _Float16 requires XMM registers.
> > >
> > > > are? (If it is restricted to SSE, we can of course ensure relevant
> > > libgcc
> > > > functions are built with SSE enabled, and likewise in glibc if that gains
> > > > _Float16 functions, though maybe with some extra complications to get
> > > > relevant testcases to run whenever possible.)
> > > >
> > >
> > > _Float16 functions in libgcc should be compiled with SSE enabled.
> > >
> > > BTW, _Float16 software emulation may require more than just SSE
> > > since we need to do _Float16 load and store with XMM registers.
> > > There is no 16bit load/store for XMM registers without AVX512FP16.
> > >
> >
> > Umm, if you just need to load/store 16-bit scalars in XMM registers you can
> > use pextrw and pinsrw which don't require AVX. f16x8 can use any of the
> > standard full-register load/stores.
>
> It looks like that requires SSE2, with SSE only inserts/extracts
> to/from MMX regs
> are supported. But of course GPR half-word loads and GPR->XMM moves of
> full size would work.
movd between sse registers and gpr also required sse2.
>
> > https://gcc.godbolt.org/z/ncznr9TM1
> >
> > Jacob
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev@lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
--
BR,
Hongtao
next prev parent reply other threads:[~2021-07-02 7:58 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-01 21:05 H.J. Lu
2021-07-01 22:10 ` Joseph Myers
2021-07-01 22:27 ` H.J. Lu
2021-07-01 22:40 ` Joseph Myers
2021-07-01 23:01 ` H.J. Lu
2021-07-01 23:05 ` [llvm-dev] " Craig Topper
2021-07-01 23:33 ` Jacob Lifshay
2021-07-02 7:45 ` Richard Biener
2021-07-02 8:03 ` Hongtao Liu [this message]
2021-07-02 9:21 ` Jakub Jelinek
2021-07-13 3:59 ` Wang, Pengfei
2021-07-13 14:26 ` H.J. Lu
2021-07-13 14:48 ` Wang, Pengfei
2021-07-13 15:04 ` H.J. Lu
2021-07-13 15:41 ` Joseph Myers
2021-07-13 16:24 ` H.J. Lu
2021-07-29 13:39 ` H.J. Lu
2021-08-24 5:55 ` John McCall
2021-08-25 12:35 ` H.J. Lu
2021-08-25 20:32 ` John McCall
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