From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by sourceware.org (Postfix) with ESMTPS id 7DEDC38CDF52 for ; Tue, 28 Jun 2022 14:39:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7DEDC38CDF52 Received: by mail-pj1-x102a.google.com with SMTP id w24so12770616pjg.5 for ; Tue, 28 Jun 2022 07:39:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ZLUxdHoc6kDUjSIZ/p5VgmLykosmP+iZb6JizDeXpNQ=; b=ytVCoXYfznY9GoZMuZrwIPcJmpmIrEORrXbFJ3GYUpA93apPF9s8gx1SxCOF5dPGue utUoPJRHVxKST5qeGslKz7ivbNPAMw3A9CRiKno8nhXDz7Nw58lR7bIu4GDryLmoxExI D8OOiZbvmJgy3xOkezKXevmTKAORvBvOr+dK7b0Al7xti5ywEKFuf92AgJhjjCz9j+TV nD1rSZTEylDaAnJX+hYwsam3DsKFXMTDpkC3a/Qp+E6kOujOsdS0vG0NR81b6IQo05t8 hnMFgVH/ddFvH+nocIhNt0HMMyNUnO6ltMol9p1sG5kICcKNUj7G1uWiWGSoRaONhq1j caww== X-Gm-Message-State: AJIora9HANeJu+yWOpSWvCofm5AQ+cWrPLRVtwtt4foA7DcMUirvYweT PA39DejH8cLxz9LTdR8kM1IkXsMa0ogtRQVAlzI= X-Google-Smtp-Source: AGRyM1vnUSVqTasWfzel/XnC7Zd5vknT/Mv5HWC2nHTYKr7mSG7xJVmvh4CyDKtZ8NRNjkVP5Z7VJfaSkV+FEHXXap0= X-Received: by 2002:a17:90b:2316:b0:1ec:7b32:55bd with SMTP id mt22-20020a17090b231600b001ec7b3255bdmr27967297pjb.217.1656427164599; Tue, 28 Jun 2022 07:39:24 -0700 (PDT) MIME-Version: 1.0 References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> <20220628040703.2296390-1-goldstein.w.n@gmail.com> In-Reply-To: <20220628040703.2296390-1-goldstein.w.n@gmail.com> From: "H.J. Lu" Date: Tue, 28 Jun 2022 07:38:47 -0700 Message-ID: Subject: Re: [PATCH v5] x86: Add more feature definitions to isa-level.h To: Noah Goldstein Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3025.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 14:39:26 -0000 On Mon, Jun 27, 2022 at 9:07 PM Noah Goldstein wrote: > > This commit doesn't change anything in itself. It is just to add > definitions that will be needed by future patches. > --- > sysdeps/x86/isa-level.h | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h > index f293aea906..77f9e2c0c3 100644 > --- a/sysdeps/x86/isa-level.h > +++ b/sysdeps/x86/isa-level.h > @@ -67,15 +67,27 @@ > /* Depending on the minimum ISA level, a feature check result can be a > compile-time constant.. */ > > + > +/* For CPU_FEATURE_USABLE_P. */ > + > /* ISA level >= 4 guaranteed includes. */ > #define AVX512F_X86_ISA_LEVEL 4 > #define AVX512VL_X86_ISA_LEVEL 4 > #define AVX512BW_X86_ISA_LEVEL 4 > +#define AVX512DQ_X86_ISA_LEVEL 4 > > /* ISA level >= 3 guaranteed includes. */ > #define AVX_X86_ISA_LEVEL 3 > #define AVX2_X86_ISA_LEVEL 3 > #define BMI2_X86_ISA_LEVEL 3 > +#define MOVBE_X86_ISA_LEVEL 3 > + > +/* ISA level >= 2 guaranteed includes. */ > +#define SSE4_2_X86_ISA_LEVEL 2 > +#define SSSE3_X86_ISA_LEVEL 2 > + > + > +/* For X86_ISA_CPU_FEATURES_ARCH_P. */ > > /* NB: This feature is enabled when ISA level >= 3, which was disabled > for the following CPUs: > @@ -89,6 +101,9 @@ > when ISA level < 3. */ > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 > > +/* Feature(s) enabled when ISA level >= 2. */ > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 > + > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P > runtime checks. They differ in two ways. > -- > 2.34.1 > LGTM. Thanks. -- H.J.