From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by sourceware.org (Postfix) with ESMTPS id 195A53858D32 for ; Wed, 15 Jun 2022 20:49:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 195A53858D32 Received: by mail-pg1-x536.google.com with SMTP id l4so11369877pgh.13 for ; Wed, 15 Jun 2022 13:49:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=fGtsEaoAPuCEIwT16odyaqDxZuky0KMzX7jy14UuCDY=; b=eG9hCaT13L95soDM0E/KY43pLHztFarceM+V4GfG3pBDL9MZyzKQYl8A8Dtpim/Mo4 Wkaoe4mi+YhWHIaQs4r18J2OmizP35EMM0cWL1K7tVa7ZKrPUbaw7U0oIAjiLXdxMcVU 3j6L2nFeU1CBTu4D4NScf4uYala6Iq6umW+T35WJynR28mSXQDCMxSR9tP2wdl+1kaTu ECrqUM05Zf7t/vxay8vIthuG9P13YMe4iUJ7hUtULBXqzjtI32/sGt0UPegTERzJ9dmW 1KNsV6kSba1u3aav98Xmqj0acgTsAH27EAb37Zz6ttVt2w8TghCGxWIWatnuYdqCgSNA nJfw== X-Gm-Message-State: AJIora+eoUumAOQiVHQXEK/T19oUkJxYPdrj7jL0A/4B+K4/j9TNDBVl atklI9pVp9jqEaep9JNCLOKkLAHwoehMkYV2MeE= X-Google-Smtp-Source: AGRyM1sFo2liK29QlLTjR574jzvXdKkYi1wxZFrtvBLn+lVUCRfMqM45ofGSZLorGWMsQnBs2dD6DOf6E0Pt8bHaneg= X-Received: by 2002:a63:1e05:0:b0:3fd:9170:800d with SMTP id e5-20020a631e05000000b003fd9170800dmr1425518pge.586.1655326161983; Wed, 15 Jun 2022 13:49:21 -0700 (PDT) MIME-Version: 1.0 References: <20220615174129.620476-2-goldstein.w.n@gmail.com> <20220615203436.3686803-1-goldstein.w.n@gmail.com> In-Reply-To: <20220615203436.3686803-1-goldstein.w.n@gmail.com> From: "H.J. Lu" Date: Wed, 15 Jun 2022 13:48:46 -0700 Message-ID: Subject: Re: [PATCH v7 2/3] x86: Add bounds `x86_non_temporal_threshold` To: Noah Goldstein Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3025.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Jun 2022 20:49:26 -0000 On Wed, Jun 15, 2022 at 1:34 PM Noah Goldstein wrote: > > The lower-bound (16448) and upper-bound (SIZE_MAX / 16) are assumed > by memmove-vec-unaligned-erms. > > The lower-bound is needed because memmove-vec-unaligned-erms unrolls > the loop aggressively in the L(large_memset_4x) case. > > The upper-bound is needed because memmove-vec-unaligned-erms > right-shifts the value of `x86_non_temporal_threshold` by > LOG_4X_MEMCPY_THRESH (4) which without a bound may overflow. > > The lack of lower-bound can be a correctness issue. The lack of > upper-bound cannot. > --- > manual/tunables.texi | 2 +- > sysdeps/x86/dl-cacheinfo.h | 8 +++++++- > 2 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/manual/tunables.texi b/manual/tunables.texi > index 1482412078..2c076019ae 100644 > --- a/manual/tunables.texi > +++ b/manual/tunables.texi > @@ -47,7 +47,7 @@ glibc.malloc.mxfast: 0x0 (min: 0x0, max: 0xffffffffffffffff) > glibc.elision.skip_lock_busy: 3 (min: -2147483648, max: 2147483647) > glibc.malloc.top_pad: 0x0 (min: 0x0, max: 0xffffffffffffffff) > glibc.cpu.x86_rep_stosb_threshold: 0x800 (min: 0x1, max: 0xffffffffffffffff) > -glibc.cpu.x86_non_temporal_threshold: 0xc0000 (min: 0x0, max: 0xffffffffffffffff) > +glibc.cpu.x86_non_temporal_threshold: 0xc0000 (min: 0x4040, max: 0x0fffffffffffffff) > glibc.cpu.x86_shstk: > glibc.cpu.hwcap_mask: 0x6 (min: 0x0, max: 0xffffffffffffffff) > glibc.malloc.mmap_max: 0 (min: -2147483648, max: 2147483647) > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h > index cc3b840f9c..e9f3382108 100644 > --- a/sysdeps/x86/dl-cacheinfo.h > +++ b/sysdeps/x86/dl-cacheinfo.h > @@ -931,8 +931,14 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > > TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, data, 0, SIZE_MAX); > TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, shared, 0, SIZE_MAX); > + /* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of > + 'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best > + if that operation cannot overflow. Minimum of 0x4040 (16448) because the > + L(large_memset_4x) loops need 64-byte to cache align and enough space for > + at least 1 iteration of 4x PAGE_SIZE unrolled loop. Both values are > + reflected in the manual. */ > TUNABLE_SET_WITH_BOUNDS (x86_non_temporal_threshold, non_temporal_threshold, > - 0, SIZE_MAX); > + 0x4040, SIZE_MAX >> 4); > TUNABLE_SET_WITH_BOUNDS (x86_rep_movsb_threshold, rep_movsb_threshold, > minimum_rep_movsb_threshold, SIZE_MAX); > TUNABLE_SET_WITH_BOUNDS (x86_rep_stosb_threshold, rep_stosb_threshold, 1, > -- > 2.34.1 > LGTM. Thanks. -- H.J.