From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by sourceware.org (Postfix) with ESMTPS id 74D4F3857414 for ; Wed, 23 Jun 2021 20:42:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 74D4F3857414 Received: by mail-pl1-x62c.google.com with SMTP id u2so1795918plf.3 for ; Wed, 23 Jun 2021 13:42:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=gRtl1W81Utnp9mvfvpP9FjV3pSBpTTZZsCC+rLNBW1o=; b=MkJSWGpXHI/nNKbg/y5oKEj41yhN/fmrs2uAJLhTIJRodILor+F/6jqqsPYp70oZLE 4YqkUMcCvvylKiCqQqbZnvMJ1TVOmYPsCc9U+INzDzj7ACDzFoOm50exNJNDQ/elUVTU vPxhec0KTA7Gs/bLYThg4G2MxYksZgpDkP438C249+RHK9XDKeecxFgvFfVG5orPEPPw L6rjFLbiSNErOhKmvwJMN8AKU5VOBIcuA6XhtNopSS6zvyYaO+fqyb2K6GgaDnwbOD5u zDj8curNvIpvLr3O5B/YKkDZf8zULhb2/VyrF6SgCS//ECMkXFVOIHhbcQ4+4VvO8RVq kGqA== X-Gm-Message-State: AOAM533Gi3yNq86zaBlhgG+hrOqpkcsnqdbU9xudHq42/dWd9eAmd8j2 o5cqVRRqQN2CNrRM0gjZcWkLrYxwQQPDu5NUjTs= X-Google-Smtp-Source: ABdhPJyyBqN/mPd8nHTvRTI+Z6BoK+yN1SIZgty2r/1RA55/ANJYnpwEiIyfQJjumAaiav4Jpn5F3gpoOhDftR7Z5DM= X-Received: by 2002:a17:902:8f8f:b029:107:810b:9ee5 with SMTP id z15-20020a1709028f8fb0290107810b9ee5mr1140701plo.4.1624480929607; Wed, 23 Jun 2021 13:42:09 -0700 (PDT) MIME-Version: 1.0 References: <20210623145419.3025540-1-adhemerval.zanella@linaro.org> In-Reply-To: <20210623145419.3025540-1-adhemerval.zanella@linaro.org> From: "H.J. Lu" Date: Wed, 23 Jun 2021 13:41:33 -0700 Message-ID: Subject: Re: [PATCH] x86: Fix tst-cpu-features-cpuinfo on Ryzen 9 (BZ #27873) To: Adhemerval Zanella Cc: GNU C Library Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3031.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Jun 2021 20:42:12 -0000 On Wed, Jun 23, 2021 at 7:54 AM Adhemerval Zanella wrote: > > AMD define different flags for IRPB, IBRS, and STIPBP [1], so new > x86_64_cpu are added and IBRS_IBPB is only tested for Intel. > > The SHSTK is also a opt-in feature, Ryzen 9 does support but the > kernel might not enable it. > > The SSDB is also defined and implemented different on AMD [2], > and also a new AMD_SSDB flag is added. It should map to the > cpuinfo 'ssdb' on recent AMD cpus. > > It fixes tst-cpu-features-cpuinfo and tst-cpu-features-cpuinfo-static > on recent AMD cpus. > > Checked on x86_64-linux-gnu on AMD Ryzen 9 5900X. > > [1] https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf > [2] https://bugzilla.kernel.org/show_bug.cgi?id=199889 > --- > sysdeps/x86/bits/platform/x86.h | 4 +++ > sysdeps/x86/include/cpu-features.h | 12 +++++++++ > sysdeps/x86/tst-cpu-features-cpuinfo.c | 35 ++++++++++++++++++++------ > 3 files changed, 43 insertions(+), 8 deletions(-) > > diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h > index fe08d8a1b6..26e3b67ede 100644 > --- a/sysdeps/x86/bits/platform/x86.h > +++ b/sysdeps/x86/bits/platform/x86.h > @@ -278,6 +278,10 @@ enum > + cpuid_register_index_ebx * 8 * sizeof (unsigned int)), > > x86_cpu_WBNOINVD = x86_cpu_index_80000008_ebx + 9, > + x86_cpu_AMD_IBPB = x86_cpu_index_80000008_ebx + 12, > + x86_cpu_AMD_IBRS = x86_cpu_index_80000008_ebx + 14, > + x86_cpu_AMD_STIBP = x86_cpu_index_80000008_ebx + 15, > + x86_cpu_AMD_SSBD = x86_cpu_index_80000008_ebx + 24, > > x86_cpu_index_7_ecx_1_eax > = (CPUID_INDEX_7_ECX_1 * 8 * 4 * sizeof (unsigned int) > diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h > index d042a2ebef..4f1c4ee402 100644 > --- a/sysdeps/x86/include/cpu-features.h > +++ b/sysdeps/x86/include/cpu-features.h > @@ -289,6 +289,10 @@ enum > > /* EBX. */ > #define bit_cpu_WBNOINVD (1u << 9) > +#define bit_cpu_AMD_IBPB (1u << 12) > +#define bit_cpu_AMD_IBRS (1u << 14) > +#define bit_cpu_AMD_STIBP (1u << 15) > +#define bit_cpu_AMD_SSBD (1u << 24) > > /* CPUID_INDEX_7_ECX_1. */ > > @@ -519,6 +523,10 @@ enum > > /* EBX. */ > #define index_cpu_WBNOINVD CPUID_INDEX_80000008 > +#define index_cpu_AMD_IBPB CPUID_INDEX_80000008 > +#define index_cpu_AMD_IBRS CPUID_INDEX_80000008 > +#define index_cpu_AMD_STIBP CPUID_INDEX_80000008 > +#define index_cpu_AMD_SSBD CPUID_INDEX_80000008 > > /* CPUID_INDEX_7_ECX_1. */ > > @@ -749,6 +757,10 @@ enum > > /* EBX. */ > #define reg_WBNOINVD ebx > +#define reg_AMD_IBPB ebx > +#define reg_AMD_IBRS ebx > +#define reg_AMD_STIBP ebx > +#define reg_AMD_SSBD ebx > > /* CPUID_INDEX_7_ECX_1. */ > > diff --git a/sysdeps/x86/tst-cpu-features-cpuinfo.c b/sysdeps/x86/tst-cpu-features-cpuinfo.c > index 75e7eb9352..6535fe50e8 100644 > --- a/sysdeps/x86/tst-cpu-features-cpuinfo.c > +++ b/sysdeps/x86/tst-cpu-features-cpuinfo.c > @@ -16,10 +16,11 @@ > License along with the GNU C Library; if not, see > . */ > > -#include > +#include > #include > #include > #include > +#include > > static char *cpu_flags; > > @@ -54,7 +55,7 @@ get_cpuinfo (void) > > int > check_proc (const char *proc_name, const char *search_name, int flag, > - int usable, const char *name) > + int usable, const char *name, bool optin) > { > int found = 0; > > @@ -78,7 +79,7 @@ check_proc (const char *proc_name, const char *search_name, int flag, > > if (found != flag) > { > - if (found || usable) > + if (!optin && (found || usable)) > printf (" *** failure ***\n"); > else > { > @@ -93,12 +94,18 @@ check_proc (const char *proc_name, const char *search_name, int flag, > #define CHECK_PROC(str, name) \ > check_proc (#str, " "#str" ", HAS_CPU_FEATURE (name), \ > CPU_FEATURE_USABLE (name), \ > - "HAS_CPU_FEATURE (" #name ")") > + "HAS_CPU_FEATURE (" #name ")", false) > + > +#define CHECK_PROC_OPTIN(str, name) \ > + check_proc (#str, " "#str" ", HAS_CPU_FEATURE (name), \ > + CPU_FEATURE_USABLE (name), \ > + "HAS_CPU_FEATURE (" #name ")", true) > > static int > do_test (int argc, char **argv) > { > int fails = 0; > + const struct cpu_features *cpu_features = __get_cpu_features (); > > get_cpuinfo (); > fails += CHECK_PROC (acpi, ACPI); > @@ -159,7 +166,17 @@ do_test (int argc, char **argv) > fails += CHECK_PROC (hle, HLE); > fails += CHECK_PROC (ht, HTT); > fails += CHECK_PROC (hybrid, HYBRID); > - fails += CHECK_PROC (ibrs, IBRS_IBPB); > + if (cpu_features->basic.kind == arch_kind_intel) > + { > + fails += CHECK_PROC (ibrs, IBRS_IBPB); > + fails += CHECK_PROC (stibp, STIBP); > + } > + else if (cpu_features->basic.kind == arch_kind_amd) > + { > + fails += CHECK_PROC (ibpb, AMD_IBPB); > + fails += CHECK_PROC (ibrs, AMD_IBRS); > + fails += CHECK_PROC (stibp, AMD_STIBP); > + } > fails += CHECK_PROC (ibt, IBT); > fails += CHECK_PROC (invariant_tsc, INVARIANT_TSC); > fails += CHECK_PROC (invpcid, INVPCID); > @@ -216,12 +233,15 @@ do_test (int argc, char **argv) > fails += CHECK_PROC (sgx, SGX); > fails += CHECK_PROC (sgx_lc, SGX_LC); > fails += CHECK_PROC (sha_ni, SHA); > - fails += CHECK_PROC (shstk, SHSTK); > + fails += CHECK_PROC_OPTIN (shstk, SHSTK); Why do you need this? If kernel doesn't support SHSTK, it will be turned off: /* Check CET status. */ unsigned int cet_status = get_cet_status (); if ((cet_status & GNU_PROPERTY_X86_FEATURE_1_IBT) == 0) CPU_FEATURE_UNSET (cpu_features, IBT) if ((cet_status & GNU_PROPERTY_X86_FEATURE_1_SHSTK) == 0) CPU_FEATURE_UNSET (cpu_features, SHSTK) > fails += CHECK_PROC (smap, SMAP); > fails += CHECK_PROC (smep, SMEP); > fails += CHECK_PROC (smx, SMX); > fails += CHECK_PROC (ss, SS); > - fails += CHECK_PROC (ssbd, SSBD); > + if (cpu_features->basic.kind == arch_kind_intel) > + fails += CHECK_PROC (ssbd, SSBD); > + else if (cpu_features->basic.kind == arch_kind_amd) > + fails += CHECK_PROC (ssbd, AMD_SSBD); > fails += CHECK_PROC (sse, SSE); > fails += CHECK_PROC (sse2, SSE2); > fails += CHECK_PROC (pni, SSE3); > @@ -229,7 +249,6 @@ do_test (int argc, char **argv) > fails += CHECK_PROC (sse4_2, SSE4_2); > fails += CHECK_PROC (sse4a, SSE4A); > fails += CHECK_PROC (ssse3, SSSE3); > - fails += CHECK_PROC (stibp, STIBP); > fails += CHECK_PROC (svm, SVM); > #ifdef __x86_64__ > /* NB: SYSCALL_SYSRET is 64-bit only. */ > -- > 2.30.2 > -- H.J.