From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by sourceware.org (Postfix) with ESMTPS id EE58F385AE47 for ; Tue, 28 Jun 2022 03:04:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EE58F385AE47 Received: by mail-pg1-x529.google.com with SMTP id x8so6269251pgj.13 for ; Mon, 27 Jun 2022 20:04:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yJhP/7GMMR819PBObynhXeNkjVTeAJgIfo+H82RzaLY=; b=AaHnVcNxVNvJOJYUWkkE/+SCIvFDqDnL/kg00/GMsnd/kZMLe769IarlewvDmtce6j 9J2CGc4vyCvmXzEEvVR0pVcu+iYpGKvIvbizYsq11baJ4uyAX96k+npAr5Yq5EOgnngh YfaiaxucxtNzvkRqxPQqJ5YhcSJt9JOkkiQ9iGOtux+AHh7/qzMrElV/+8OUbZfhS53w v8SCdL1bEengm/V5eKabgk8na1ZY1ORSafl4IGfys8JKYzqWhtlyxvvUy1S5yASL225Q IDD2K9sS/VnV+V3ZAalx6/gihNiBf8Hm2CLFGpC8v5gOEmfW7CCbeXGNaZURAg9ei69r XypA== X-Gm-Message-State: AJIora/UAI4FWjs/X1SEX4kDR74aSOyg1W0AYAjowoP8U91vctXUr3CT /x64lPBkTbWFgO5RDJ1LCG9btaA45TSxksOBQWg= X-Google-Smtp-Source: AGRyM1smGdxdxmRJD8m1/Vg+nTgLtkOkoj6vQ9tKg0bJQZi7tgisICcy9C26bM3cF7TU3YlU35GUf/XeZUb0KUapp28= X-Received: by 2002:a05:6a00:c:b0:525:55cb:83cd with SMTP id h12-20020a056a00000c00b0052555cb83cdmr2383681pfk.20.1656385450925; Mon, 27 Jun 2022 20:04:10 -0700 (PDT) MIME-Version: 1.0 References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> <20220628020342.213807-1-goldstein.w.n@gmail.com> In-Reply-To: From: "H.J. Lu" Date: Mon, 27 Jun 2022 20:03:34 -0700 Message-ID: Subject: Re: [PATCH v2] x86: Add more feature definitions to isa-level.h To: Noah Goldstein Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3025.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 03:04:13 -0000 On Mon, Jun 27, 2022 at 7:42 PM Noah Goldstein wrote: > > On Mon, Jun 27, 2022 at 7:39 PM H.J. Lu wrote: > > > > On Mon, Jun 27, 2022 at 7:34 PM Noah Goldstein wrote: > > > > > > On Mon, Jun 27, 2022 at 7:30 PM H.J. Lu wrote: > > > > > > > > On Mon, Jun 27, 2022 at 7:03 PM Noah Goldstein wrote: > > > > > > > > > > This commit doesn't change anything in itself. It is just to add > > > > > definitions that will be needed by future patches. > > > > > --- > > > > > sysdeps/x86/isa-level.h | 10 ++++++++++ > > > > > 1 file changed, 10 insertions(+) > > > > > > > > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h > > > > > index f293aea906..024d1deb80 100644 > > > > > --- a/sysdeps/x86/isa-level.h > > > > > +++ b/sysdeps/x86/isa-level.h > > > > > @@ -71,11 +71,13 @@ > > > > > #define AVX512F_X86_ISA_LEVEL 4 > > > > > #define AVX512VL_X86_ISA_LEVEL 4 > > > > > #define AVX512BW_X86_ISA_LEVEL 4 > > > > > +#define AVX512DQ_X86_ISA_LEVEL 4 > > > > > > > > > > /* ISA level >= 3 guaranteed includes. */ > > > > > #define AVX_X86_ISA_LEVEL 3 > > > > > #define AVX2_X86_ISA_LEVEL 3 > > > > > #define BMI2_X86_ISA_LEVEL 3 > > > > > +#define MOVBE_X86_ISA_LEVEL 3 > > > > > > > > > > /* NB: This feature is enabled when ISA level >= 3, which was disabled > > > > > for the following CPUs: > > > > > @@ -89,6 +91,14 @@ > > > > > when ISA level < 3. */ > > > > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 > > > > > > > > > > +/* ISA level >= 2 guaranteed includes. */ > > > > > > Have a comment for ISA level 2 here. > > > > ISA is included. But arch features can be enabled/disabled. > > > > > > > +#define SSE4_2_X86_ISA_LEVEL 2 > > > > > +#define SSSE3_X86_ISA_LEVEL 2 > > > > > + > > > > > +/* NB: This feature is enabled when ISA level >= 2. No CPUs should be > > > > > + affected by this. */ > > > > > > > > /* Features enabled when ISA level >= 2. */ > > > > > > Hm? This is singular. > > > > Will more be added? > > None for this patchset. If in the future there are (with the same > affected CPU set) > I will make the comment plural. Use singular then. > > > > > > > > > > > > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 > > > > > + > > > > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P > > > > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P > > > > > runtime checks. They differ in two ways. > > > > > -- > > > > > 2.34.1 > > > > > > > > > > > > > > > > > -- > > > > H.J. > > > > > > > > -- > > H.J. -- H.J.