From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by sourceware.org (Postfix) with ESMTPS id 7953C3857827 for ; Tue, 28 Jun 2022 01:57:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7953C3857827 Received: by mail-pg1-x52d.google.com with SMTP id h192so10784912pgc.4 for ; Mon, 27 Jun 2022 18:57:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0ZsZUsRm0jZBUczuN/+OZrbz7HKIfxKvaw9l0a0Cras=; b=vF037zQhcXm/KvuTahfODKzku74dUArWPjwDwpJW0AMDnw4X1OGsSSYRs3wNadMcqE DQttjA7zjD1lgqUFVw2ecsyO3BJepfk/CuQkwITSwUfz3X8W2V2FJGPDOzvxOvo13byv BA7+Fnfmv9dGhvcft05rne1bRSTqI06rVErU5athd2HZOfQHaD4xSKoJuPdkkEK9QcOQ /j1oBdQJ/tGFQlPPe3VBT64npycmbAiFpIfJdtjL2R6wbkYrggBWw7CeqwNbXZLV62LY bHEPp5a3wIal8tK9Rm6rv+yNvUzLWtl30XgzSJTuHCPCo+/PxrraUbsh2c2na0hLlDOr w7kw== X-Gm-Message-State: AJIora+KjjjfYo0MKchKjdDFEFGSIMjfeLX1vfvLTBbMyMbu2PUfA5ru a98SWf7kYae3ciUZaFw5NHckrl2LCjlBIpuJd1lc7E3vU1w= X-Google-Smtp-Source: AGRyM1tODvgcM5L4F8180//nDvEZ6Aoskxbf+pnYCRIVmq3qQP+bhpgK9AzVjGC2jTCFO+Ug/asKDwt/d8rTyWiFOSU= X-Received: by 2002:a63:b54c:0:b0:40c:7b84:4f7f with SMTP id u12-20020a63b54c000000b0040c7b844f7fmr14956756pgo.586.1656381442485; Mon, 27 Jun 2022 18:57:22 -0700 (PDT) MIME-Version: 1.0 References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> In-Reply-To: <20220628010446.3464287-1-goldstein.w.n@gmail.com> From: "H.J. Lu" Date: Mon, 27 Jun 2022 18:56:46 -0700 Message-ID: Subject: Re: [PATCH v1] x86: Add more feature definitions to isa-level.h To: Noah Goldstein Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3024.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 01:57:24 -0000 On Mon, Jun 27, 2022 at 6:05 PM Noah Goldstein wrote: > > This commit doesn't change anything in itself. It is just to add > definitions that will be needed by future patches. > --- > sysdeps/x86/isa-level.h | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h > index f293aea906..f5ca625c21 100644 > --- a/sysdeps/x86/isa-level.h > +++ b/sysdeps/x86/isa-level.h > @@ -71,11 +71,13 @@ > #define AVX512F_X86_ISA_LEVEL 4 > #define AVX512VL_X86_ISA_LEVEL 4 > #define AVX512BW_X86_ISA_LEVEL 4 > +#define AVX512DQ_X86_ISA_LEVEL 4 > > /* ISA level >= 3 guaranteed includes. */ > #define AVX_X86_ISA_LEVEL 3 > #define AVX2_X86_ISA_LEVEL 3 > #define BMI2_X86_ISA_LEVEL 3 > +#define MOVBE_X86_ISA_LEVEL 3 > > /* NB: This feature is enabled when ISA level >= 3, which was disabled > for the following CPUs: > @@ -89,6 +91,11 @@ > when ISA level < 3. */ > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 > > +/* ISA level >= 2 guaranteed includes. */ > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 This should be defined as enabled/disabled, similarly to AVX_Fast_Unaligned_Load_X86_ISA_LEVEL. > +#define SSE4_2_X86_ISA_LEVEL 2 > +#define SSSE3_X86_ISA_LEVEL 2 > + > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P > runtime checks. They differ in two ways. > -- > 2.34.1 > -- H.J.