From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by sourceware.org (Postfix) with ESMTPS id 23D5D385AE47 for ; Tue, 28 Jun 2022 03:59:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 23D5D385AE47 Received: by mail-pf1-x42f.google.com with SMTP id t21so10875038pfq.1 for ; Mon, 27 Jun 2022 20:59:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=g7rsBAJY/SeegxHCN4Tgc19ivSVrAvfwoIhUS7+ifNg=; b=T75iZ+Cjnl86C9n6roIbsWsyLHMdZ5Up792/xLWzdejjkUZtN23OpqJuIO9uAxLUZE Dbw1j1OAWmV8O6qHop/ISug8/8tlFdkrgIAIE5ZQxwqf+dUqq/BSwpwO0Cx0XFZCjSY9 GamqcuWwGXlkMrpYM6e+otKCXHO2pTLkcwWifsia11XR/gApF/mqW3l5sCmzXgVFMh2j auCasVYButFha7EVWDVI+om888n+50RAHj3BZH3Dz0U6foEl0XNRrKfRXJ7WMKD1DhYC l3LpqJ8PtxQYBROAHX7quT/kyecV9CMG8/4Tyg/L8YATdl2Oo99qBFKyLKcaPUdRRzLa ePBw== X-Gm-Message-State: AJIora/ixxxwwe2dGhjDbtr53NZG6QlZECpNlVuBdwdUvUZQQhOsnODQ 1rim6qrkaGKdC11emcA+3HEn2kr0nGbBkimrJ0E= X-Google-Smtp-Source: AGRyM1uPv9KsC4z+gFoLAWa9R7o05c6n6wdTLdmYptqT+ZzQ8eHMDdgq/Y6pXH7dhsSLdF49DeLbqS07YPGC7xXJ1kc= X-Received: by 2002:a63:b54c:0:b0:40c:7b84:4f7f with SMTP id u12-20020a63b54c000000b0040c7b844f7fmr15334650pgo.586.1656388762198; Mon, 27 Jun 2022 20:59:22 -0700 (PDT) MIME-Version: 1.0 References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> <20220628034939.2116112-1-goldstein.w.n@gmail.com> In-Reply-To: <20220628034939.2116112-1-goldstein.w.n@gmail.com> From: "H.J. Lu" Date: Mon, 27 Jun 2022 20:58:46 -0700 Message-ID: Subject: Re: [PATCH v4] x86: Add more feature definitions to isa-level.h To: Noah Goldstein Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3024.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 03:59:26 -0000 On Mon, Jun 27, 2022 at 8:49 PM Noah Goldstein wrote: > > This commit doesn't change anything in itself. It is just to add > definitions that will be needed by future patches. > --- > sysdeps/x86/isa-level.h | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h > index f293aea906..2cbce25840 100644 > --- a/sysdeps/x86/isa-level.h > +++ b/sysdeps/x86/isa-level.h > @@ -67,15 +67,29 @@ > /* Depending on the minimum ISA level, a feature check result can be a > compile-time constant.. */ > > + > +/* ISA CPU_FEATURE_USABLE_P defaults. */ What does "defaults" mean? "For X86_ISA_CPU_FEATURE_USABLE_P"? > + > /* ISA level >= 4 guaranteed includes. */ > #define AVX512F_X86_ISA_LEVEL 4 > #define AVX512VL_X86_ISA_LEVEL 4 > #define AVX512BW_X86_ISA_LEVEL 4 > +#define AVX512DQ_X86_ISA_LEVEL 4 > > /* ISA level >= 3 guaranteed includes. */ > #define AVX_X86_ISA_LEVEL 3 > #define AVX2_X86_ISA_LEVEL 3 > #define BMI2_X86_ISA_LEVEL 3 > +#define MOVBE_X86_ISA_LEVEL 3 > + > +/* ISA level >= 2 guaranteed includes. */ > +#define SSE4_2_X86_ISA_LEVEL 2 > +#define SSSE3_X86_ISA_LEVEL 2 > + > + > +/* ISA CPU_FEATURES_ARCH_P defaults. */ "For X86_ISA_CPU_FEATURES_ARCH_P"? > + > +/* Isa level >= 3 feature(s) enabled. */ No need for this. Some features may be disabled. > > /* NB: This feature is enabled when ISA level >= 3, which was disabled > for the following CPUs: > @@ -89,6 +103,9 @@ > when ISA level < 3. */ > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 > > +/* Isa level >= 2 feature(s) enabled. */ These are not features in ISAs. "Feature(s) enabled when ISA level >= 2"? > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 > + > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P > runtime checks. They differ in two ways. > -- > 2.34.1 > -- H.J.