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References: <20220624164216.2129400-1-goldstein.w.n@gmail.com>
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From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Fri, 24 Jun 2022 10:15:17 -0700
Message-ID: <CAMe9rOpa6e7+9uD05d8B-C-iJ8HmPvr4TSNOxzoTupt_afUSzg@mail.gmail.com>
Subject: Re: [PATCH v2] x86: Align entry for memrchr to 64-bytes.
To: Noah Goldstein <goldstein.w.n@gmail.com>
Cc: GNU C Library <libc-alpha@sourceware.org>,
 "Carlos O'Donell" <carlos@systemhalted.org>
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On Fri, Jun 24, 2022 at 9:42 AM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> The function was tuned around 64-byte entry alignment and performs
> better for all sizes with it.
>
> As well different code boths where explicitly written to touch the
> minimum number of cache line i.e sizes <= 32 touch only the entry
> cache line.
> ---
>  sysdeps/x86_64/multiarch/memrchr-avx2.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/sysdeps/x86_64/multiarch/memrchr-avx2.S b/sysdeps/x86_64/multiarch/memrchr-avx2.S
> index 9c83c76d3c..f300d7daf4 100644
> --- a/sysdeps/x86_64/multiarch/memrchr-avx2.S
> +++ b/sysdeps/x86_64/multiarch/memrchr-avx2.S
> @@ -35,7 +35,7 @@
>  # define VEC_SIZE                      32
>  # define PAGE_SIZE                     4096
>         .section SECTION(.text), "ax", @progbits
> -ENTRY(MEMRCHR)
> +ENTRY_P2ALIGN(MEMRCHR, 6)
>  # ifdef __ILP32__
>         /* Clear upper bits.  */
>         and     %RDX_LP, %RDX_LP
> --
> 2.34.1
>

LGTM.

Thanks.

-- 
H.J.