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References: <20200819104539.9854-1-sajan.karumanchi@amd.com>
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In-Reply-To: <20200819104539.9854-2-sajan.karumanchi@amd.com>
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Tue, 1 Sep 2020 12:23:23 -0700
Message-ID: <CAMe9rOps7kfcZQY4jER6Y24U3vt5CesFa97La7HyTW98aTrqvA@mail.gmail.com>
Subject: Re: [PATCH 1/1] x86: Tuning NT Threshold parameter for AMD machines.
To: Sajan Karumanchi <sajan.karumanchi@gmail.com>
Cc: GNU C Library <libc-alpha@sourceware.org>,
 "Carlos O'Donell" <carlos@redhat.com>, 
 Sajan Karumanchi <sajan.karumanchi@amd.com>, 
 "Mallappa, Premachandra" <premachandra.mallappa@amd.com>
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On Wed, Aug 19, 2020 at 3:58 AM Sajan Karumanchi via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> Tuning NT threshold parameter to bring in performance gains of
> memcpy/memove on AMD cpu's.
>
> Based on Large and Walk bench variant results,
> setting __x86_shared_non_temporal_threshold to 2/3 of shared cache size
> brings in performance gains for memcpy/memmove on AMD machines.
>

The patch looks mostly OK.  But I have quite a few x86 patches queued
which touch the same codes.  Please take a look at

https://gitlab.com/x86-glibc/glibc/-/commits/users/hjl/tunable/master

and put your patch on top of mine.

-- 
H.J.