From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-il1-x141.google.com (mail-il1-x141.google.com [IPv6:2607:f8b0:4864:20::141]) by sourceware.org (Postfix) with ESMTPS id 7A6D938930F7 for ; Fri, 24 Apr 2020 12:54:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 7A6D938930F7 Received: by mail-il1-x141.google.com with SMTP id u5so9161819ilb.5 for ; Fri, 24 Apr 2020 05:54:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=lVKQw6hqgzv/xwBc5xy2mbh2tN/rpZhnXzRR0hvhWas=; b=YK+s+wxMnk21QvH178F4wpOyd6Kw9WJT1Ag4FoDGAOTV1VM2BTgthH4+LAiaC7PIl8 RZ/A0+uZne1G3k0ARXLt8alrJoxuBTZp1H7v3Q/RKQo6gmjeMocrchLb1CChxjx31KNp kNgeuUFNbLlsgEW7YXXjYvJGnXv7Ojxl6MoUYxPZiG1lbu1zJUCQGqK8s4TgTisdRA3V A9vjqmhs6a5jqPpsQ3p18/ir/a20MY9CuOTDajzF8KTUT+qRXJdO8UrLElGqNLzqrXwk C2Koqzht2qmf5ZLKqNpQuNJF/wTz4gTagApWfSojQcwHte8FgYGXB5Vz0egbPbPyituG wDjg== X-Gm-Message-State: AGi0PuZ0ZdXoKIJ0mcLrFW6GeDWr6+Vk6JEDrlghU57rM3z4lpsmzcom MVADIoCpnnZUvplreaJ5eCJ9sli83UKr1q8VOQI= X-Google-Smtp-Source: APiQypLLdd/rXkATS3I1aNMiqIfcylTXer5++p6qkiBkps3gmDHVAg2fZnsOPGX4xqxuNDNxwcMtShCtu9KbK5aCLIg= X-Received: by 2002:a92:d149:: with SMTP id t9mr7925642ilg.213.1587732850007; Fri, 24 Apr 2020 05:54:10 -0700 (PDT) MIME-Version: 1.0 References: <1587731372-9324-1-git-send-email-mayshao-oc@zhaoxin.com> <1587731372-9324-2-git-send-email-mayshao-oc@zhaoxin.com> In-Reply-To: <1587731372-9324-2-git-send-email-mayshao-oc@zhaoxin.com> From: "H.J. Lu" Date: Fri, 24 Apr 2020 05:53:34 -0700 Message-ID: Subject: Re: [PATCH v3 1/3] x86: Add CPU Vendor ID detection support for Zhaoxin processors To: mayshao-oc Cc: GNU C Library , "Carlos O'Donell" , Florian Weimer , "Qiyuan Wang(BJ-RD)" , "Herry Yang(BJ-RD)" , "Ricky Li(BJ-RD)" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-18.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Apr 2020 12:54:11 -0000 On Fri, Apr 24, 2020 at 5:29 AM mayshao-oc wrote: > > From: mayshao > > To recognize Zhaoxin CPU Vendor ID, add a new architecture type > arch_kind_zhaoxin for Vendor Zhaoxin detection. > --- > sysdeps/x86/cpu-features.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ > sysdeps/x86/cpu-features.h | 1 + > 2 files changed, 55 insertions(+) > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > index 81a170a..bfb415f 100644 > --- a/sysdeps/x86/cpu-features.c > +++ b/sysdeps/x86/cpu-features.c > @@ -466,6 +466,60 @@ init_cpu_features (struct cpu_features *cpu_features) > } > } > } > + /* This spells out "CentaurHauls" or " Shanghai ". */ > + else if ((ebx == 0x746e6543 && ecx == 0x736c7561 && edx == 0x48727561) > + || (ebx == 0x68532020 && ecx == 0x20206961 && edx == 0x68676e61)) > + { > + unsigned int extended_model, stepping; > + > + kind = arch_kind_zhaoxin; > + > + get_common_indices (cpu_features, &family, &model, &extended_model, > + &stepping); > + > + get_extended_indices (cpu_features); > + > + model += extended_model; > + if (family == 0x6) > + { > + if (model == 0xf || model == 0x19) > + { > + cpu_features->feature[index_arch_AVX_Usable] > + &= (~bit_arch_AVX_Usable > + & ~bit_arch_AVX2_Usable); > + > + cpu_features->feature[index_arch_Slow_SSE4_2] > + |= (bit_arch_Slow_SSE4_2); > + > + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] > + &= ~bit_arch_AVX_Fast_Unaligned_Load; > + } > + } > + else if (family == 0x7) > + { > + if (model == 0x1b) > + { > + cpu_features->feature[index_arch_AVX_Usable] > + &= (~bit_arch_AVX_Usable > + & ~bit_arch_AVX2_Usable); > + > + cpu_features->feature[index_arch_Slow_SSE4_2] > + |= bit_arch_Slow_SSE4_2; > + > + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] > + &= ~bit_arch_AVX_Fast_Unaligned_Load; > + } > + else if (model == 0x3b) > + { > + cpu_features->feature[index_arch_AVX_Usable] > + &= (~bit_arch_AVX_Usable > + & ~bit_arch_AVX2_Usable); > + > + cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load] > + &= ~bit_arch_AVX_Fast_Unaligned_Load; > + } > + } > + } > else > { > kind = arch_kind_other; > diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h > index aea83e6..f05d5ce 100644 > --- a/sysdeps/x86/cpu-features.h > +++ b/sysdeps/x86/cpu-features.h > @@ -53,6 +53,7 @@ enum cpu_features_kind > arch_kind_unknown = 0, > arch_kind_intel, > arch_kind_amd, > + arch_kind_zhaoxin, > arch_kind_other > }; > > -- > 2.7.4 > LGTM. -- H.J.