From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by sourceware.org (Postfix) with ESMTPS id E43E2383D80B for ; Fri, 24 Jun 2022 17:03:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E43E2383D80B Received: by mail-pl1-x635.google.com with SMTP id q18so2584965pld.13 for ; Fri, 24 Jun 2022 10:03:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VW5XSj94DBbNjW8z0IwxzT8AboNrGkLo1XH4YKu9Fek=; b=8Roda0AMCh5llllHy2Th4Wsx8kbAwKWJy591Jsd6O2RykI6AzPBhgRQauCbJavUcsi WuYvsFpBPDWnMziRS9crUtQOqr9XI8U9aOjGfiLzYcQX7c+vW+MPs28tP0RE4MqyjI8M Hw24JmzA+Gq0tMbLA5HPeg0wqc6WV3EmQDeD52Yo2rQV0RhyvE3GkTny0VMw+coKlm76 Q/5MzjcW5ePmLzBEvssNmfZBGTxSb6i5mszTzbu/Y/m6bsxOauPO+CMeRrcTKwY+g0Ct Gm5CwJFLsf/nWioR2FYwBXFNLYbeE2Lo4t6/Ag9/ec9A6ZgT/s6vFdNRedb11epVv63w 0XFQ== X-Gm-Message-State: AJIora/EdUgXdIT1Fw0Had6cPuRDd/Ipk09CXBUIjF2FqJdI4O9jIK4J JcUhESabKPFKAomPvnPLPeX/UyVj+Vd6BMB+9lw= X-Google-Smtp-Source: AGRyM1vK+WLf1z+1tD/DqiOkX5VdHnimos4pT/8Ifu/8f59q/QSo56JotnTiNMYM4xLCvZrYE2uDITY3T/yRFS3STa0= X-Received: by 2002:a17:902:7088:b0:167:78c0:e05e with SMTP id z8-20020a170902708800b0016778c0e05emr19415plk.149.1656090194642; Fri, 24 Jun 2022 10:03:14 -0700 (PDT) MIME-Version: 1.0 References: <20220624164216.2129400-1-goldstein.w.n@gmail.com> <20220624164216.2129400-5-goldstein.w.n@gmail.com> In-Reply-To: <20220624164216.2129400-5-goldstein.w.n@gmail.com> From: "H.J. Lu" Date: Fri, 24 Jun 2022 10:02:38 -0700 Message-ID: Subject: Re: [PATCH v2] x86: Add comment with ISA level for all targets support by GCC12.1 To: Noah Goldstein Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3024.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Jun 2022 17:03:18 -0000 On Fri, Jun 24, 2022 at 9:42 AM Noah Goldstein wrote: > > This is just a quality of life change to make it easier to see how the > ISA level will effect a given build. > --- > sysdeps/x86/isa-level.h | 67 +++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 65 insertions(+), 2 deletions(-) > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h > index e1a30ed83e..f14ae5cc00 100644 > --- a/sysdeps/x86/isa-level.h > +++ b/sysdeps/x86/isa-level.h > @@ -64,8 +64,71 @@ > #define MINIMUM_X86_ISA_LEVEL \ > (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4) > > - > -/* > +/* ISA levels for known GCC targets as of GCC12.1: > + * > + * amdfam10 -> 1 > + * athlon-fx -> 1 > + * athlon64 -> 1 > + * athlon64-sse3 -> 1 > + * atom -> 1 > + * barcelona -> 1 > + * bonnell -> 1 > + * btver1 -> 1 > + * core2 -> 1 > + * eden-x2 -> 1 > + * eden-x4 -> 1 > + * k8 -> 1 > + * k8-sse3 -> 1 > + * nano -> 1 > + * nano-1000 -> 1 > + * nano-2000 -> 1 > + * nano-3000 -> 1 > + * nano-x2 -> 1 > + * nano-x4 -> 1 > + * nocona -> 1 > + * opteron -> 1 > + * opteron-sse3 -> 1 > + * x86-64 -> 1 > + * bdver1 -> 2 > + * bdver2 -> 2 > + * bdver3 -> 2 > + * btver2 -> 2 > + * core-avx-i -> 2 > + * corei7 -> 2 > + * corei7-avx -> 2 > + * goldmont -> 2 > + * goldmont-plus -> 2 > + * ivybridge -> 2 > + * nehalem -> 2 > + * sandybridge -> 2 > + * silvermont -> 2 > + * slm -> 2 > + * tremont -> 2 > + * westmere -> 2 > + * x86-64-v2 -> 2 > + * alderlake -> 3 > + * bdver4 -> 3 > + * broadwell -> 3 > + * core-avx2 -> 3 > + * haswell -> 3 > + * knl -> 3 > + * knm -> 3 > + * skylake -> 3 > + * x86-64-v3 -> 3 > + * znver1 -> 3 > + * znver2 -> 3 > + * znver3 -> 3 > + * cannonlake -> 4 > + * cascadelake -> 4 > + * cooperlake -> 4 > + * icelake-client -> 4 > + * icelake-server -> 4 > + * rocketlake -> 4 > + * sapphirerapids -> 4 > + * skylake-avx512 -> 4 > + * tigerlake -> 4 > + * x86-64-v4 -> 4 > + * > * CPU Features that are hard coded as enabled/disabled depending on > * ISA build level. > * - Values > 0 features are always ENABLED if: > -- > 2.34.1 > I don't think it is needed. -- H.J.