From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x230.google.com (mail-oi1-x230.google.com [IPv6:2607:f8b0:4864:20::230]) by sourceware.org (Postfix) with ESMTPS id 69A143836C1A for ; Mon, 1 Feb 2021 17:06:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 69A143836C1A Received: by mail-oi1-x230.google.com with SMTP id j25so19576868oii.0 for ; Mon, 01 Feb 2021 09:06:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=09DMsVsxPu3AmoG3VlSVcTmnXCeQPyg/yLjHJ81SoEM=; b=r9uIbiQ6LIowLFljE7aE6bYzPkvKobIGtpL9ATisx3aervczSRZHVxTYB9gKqp6Nwc h0vwbgE5/yA5pyEZQCFBOGGF73Jteii5c0LD882Wg/jbtj9iwfGg2JT7ECA5CKRJXyLv fb11ssukU19I8rrTx7nI00YxuPey/+WDXCGSq8JHo95hIavlIJtC3v4AjMfG8j7qilmE M4GWeCCk/7hkaRSH5CZdU8FmOZR00dCGzLCoVDVKY6APh1JXM5q2H9Onckc7d9ysPvkZ gu9gyuuAD7i+qniOHsUgHWjA1yAzL7WIZ85QWiAvQDJbNwy4DvguXAlXRdeomM6XRpto rM9w== X-Gm-Message-State: AOAM531TwhJKxfFdxq/Y5yIC/PaLjD4mJBOAUsaVVNxu3kXEpCy6jXNB vNafnw4TYON2JfvWgGzEWJ/kzTp/f5Q71ZfbZIQ= X-Google-Smtp-Source: ABdhPJwPLxYuKhONGmjeEnLYtCe4+ieZ5xqoLLNeXFqOeJJS7Ev9T6PTBItwGZA69ssPzsSVeeZyroi//upjfUYDHiQ= X-Received: by 2002:aca:f503:: with SMTP id t3mr11762353oih.79.1612199170813; Mon, 01 Feb 2021 09:06:10 -0800 (PST) MIME-Version: 1.0 References: <87wnwamax7.fsf@oldenburg.str.redhat.com> <20210122101850.3028846-1-sajan.karumanchi@amd.com> In-Reply-To: <20210122101850.3028846-1-sajan.karumanchi@amd.com> From: "H.J. Lu" Date: Mon, 1 Feb 2021 09:05:34 -0800 Message-ID: Subject: Re: [PATCH] x86: Adding an upper bound for Enhanced REP MOVSB. To: Sajan Karumanchi Cc: Florian Weimer , GNU C Library , "Carlos O'Donell" , Premachandra Mallappa Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3036.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 01 Feb 2021 17:06:13 -0000 On Fri, Jan 22, 2021 at 2:19 AM wrote: > > From: Sajan Karumanchi > > In the process of optimizing memcpy for AMD machines, we have found the > vector move operations are outperforming enhanced REP MOVSB for data > transfers above the L2 cache size on Zen3 architectures. > To handle this use case, we are adding an upper bound parameter on > enhanced REP MOVSB:'__x86_rep_movsb_stop_threshold'. > As per large-bench results, we are configuring this parameter to the > L2 cache size for AMD machines and applicable from Zen3 architecture > supporting the ERMS feature. > For architectures other than AMD, it is the computed value of > non-temporal threshold parameter. > > Reviewed-by: Premachandra Mallappa > --- > sysdeps/x86/cacheinfo.h | 4 ++++ > sysdeps/x86/dl-cacheinfo.h | 15 ++++++++++++++- > sysdeps/x86/include/cpu-features.h | 2 ++ > .../x86_64/multiarch/memmove-vec-unaligned-erms.S | 7 +++++-- > 4 files changed, 25 insertions(+), 3 deletions(-) > > diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h > index 68c253542f..0f0ca7c08c 100644 > --- a/sysdeps/x86/cacheinfo.h > +++ b/sysdeps/x86/cacheinfo.h > @@ -54,6 +54,9 @@ long int __x86_rep_movsb_threshold attribute_hidden = 2048; > /* Threshold to use Enhanced REP STOSB. */ > long int __x86_rep_stosb_threshold attribute_hidden = 2048; > > +/* Threshold to stop using Enhanced REP MOVSB. */ > +long int __x86_rep_movsb_stop_threshold attribute_hidden; > + > static void > init_cacheinfo (void) > { > @@ -79,5 +82,6 @@ init_cacheinfo (void) > > __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold; > __x86_rep_stosb_threshold = cpu_features->rep_stosb_threshold; > + __x86_rep_movsb_stop_threshold = cpu_features->rep_movsb_stop_threshold; > } > #endif > diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h > index a31fa0783a..374ba82467 100644 > --- a/sysdeps/x86/dl-cacheinfo.h > +++ b/sysdeps/x86/dl-cacheinfo.h > @@ -704,7 +704,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > int max_cpuid_ex; > long int data = -1; > long int shared = -1; > - long int core; > + long int core = -1; > unsigned int threads = 0; > unsigned long int level1_icache_size = -1; > unsigned long int level1_dcache_size = -1; > @@ -886,6 +886,18 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > #endif > } > > + unsigned long int rep_movsb_stop_threshold; > + /* ERMS feature is implemented from AMD Zen3 architecture and it is > + performing poorly for data above L2 cache size. Henceforth, adding > + an upper bound threshold parameter to limit the usage of Enhanced > + REP MOVSB operations and setting its value to L2 cache size. */ > + if (cpu_features->basic.kind == arch_kind_amd) > + rep_movsb_stop_threshold = core; > + /* Setting the upper bound of ERMS to the computed value of > + non-temporal threshold for architectures other than AMD. */ > + else > + rep_movsb_stop_threshold = non_temporal_threshold; > + > /* The default threshold to use Enhanced REP STOSB. */ > unsigned long int rep_stosb_threshold = 2048; > > @@ -935,4 +947,5 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) > cpu_features->non_temporal_threshold = non_temporal_threshold; > cpu_features->rep_movsb_threshold = rep_movsb_threshold; > cpu_features->rep_stosb_threshold = rep_stosb_threshold; > + cpu_features->rep_movsb_stop_threshold = rep_movsb_stop_threshold; > } > diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h > index 624736b40e..475e877294 100644 > --- a/sysdeps/x86/include/cpu-features.h > +++ b/sysdeps/x86/include/cpu-features.h > @@ -870,6 +870,8 @@ struct cpu_features > unsigned long int non_temporal_threshold; > /* Threshold to use "rep movsb". */ > unsigned long int rep_movsb_threshold; > + /* Threshold to stop using "rep movsb". */ > + unsigned long int rep_movsb_stop_threshold; > /* Threshold to use "rep stosb". */ > unsigned long int rep_stosb_threshold; > /* _SC_LEVEL1_ICACHE_SIZE. */ > diff --git a/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S > index 0980c95378..50bb1fccb2 100644 > --- a/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S > +++ b/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S > @@ -30,7 +30,10 @@ > load and aligned store. Load the last 4 * VEC and first VEC > before the loop and store them after the loop to support > overlapping addresses. > - 6. If size >= __x86_shared_non_temporal_threshold and there is no > + 6. On machines with ERMS feature, if size greater than equal or to > + __x86_rep_movsb_threshold and less than > + __x86_rep_movsb_stop_threshold, then REP MOVSB will be used. > + 7. If size >= __x86_shared_non_temporal_threshold and there is no > overlap between destination and source, use non-temporal store > instead of aligned store. */ > > @@ -240,7 +243,7 @@ L(return): > ret > > L(movsb): > - cmp __x86_shared_non_temporal_threshold(%rip), %RDX_LP > + cmp __x86_rep_movsb_stop_threshold(%rip), %RDX_LP > jae L(more_8x_vec) > cmpq %rsi, %rdi > jb 1f > -- > 2.25.1 > LGTM. OK for 2.34. Thanks. -- H.J.