From: "H.J. Lu" <hjl.tools@gmail.com>
To: Andrew Senkevich <andrew.n.senkevich@gmail.com>
Cc: libc-alpha <libc-alpha@sourceware.org>
Subject: Re: [PATCH] [x86_64] Detection of availability of AVX512F and AVX512DQ ISAs
Date: Wed, 29 Apr 2015 15:17:00 -0000 [thread overview]
Message-ID: <CAMe9rOqrrUwUx7BrWRwHHLvMtt19er27XCnyoxSwSy7XzC9bUg@mail.gmail.com> (raw)
In-Reply-To: <CAMXFM3tt+9NG7vdZowDdMrmWWKtKGWhBW2Q3NL2mddXO+pkjGg@mail.gmail.com>
On Wed, Apr 29, 2015 at 8:10 AM, Andrew Senkevich
<andrew.n.senkevich@gmail.com> wrote:
> Hi,
>
> this patch adds detection of availability of AVX512F and AVX512DQ ISAs.
>
> 2015-04-29 Andrew Senkevich <andrew.senkevich@intel.com>
>
> * sysdeps/x86_64/multiarch/init-arch.h (bit_AVX512F_Usable,
> bit_AVX512DQ_Usable): New macro.
> * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features):
> Check and set bit_AVX512F_Usable, bit_AVX512DQ_Usable.
>
> diff --git a/sysdeps/x86_64/multiarch/init-arch.c
> b/sysdeps/x86_64/multiarch/init-arch.c
> index 7dec218..6a81d48 100644
> --- a/sysdeps/x86_64/multiarch/init-arch.c
> +++ b/sysdeps/x86_64/multiarch/init-arch.c
> @@ -179,6 +179,19 @@ __init_cpu_features (void)
> if (CPUID_AVX2)
> __cpu_features.feature[index_AVX2_Usable]
> |= bit_AVX2_Usable | bit_AVX_Fast_Unaligned_Load;
> + /* Check if OPMASK state, upper 256-bit of ZMM0-ZMM15 and
> + ZMM16-ZMM31 state are enabled. */
> + if ((xcrlow & 0xe0) == 0xe0 )
Please add/use bit_ZMM0_15_state and bit_ZMM16_31_state.
This file is used by both 32-bit and 64-bit. Does it work for both
32-bit and 64-bit?
--
H.J.
next prev parent reply other threads:[~2015-04-29 15:17 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-29 15:11 Andrew Senkevich
2015-04-29 15:17 ` H.J. Lu [this message]
2015-05-27 11:12 ` Andrew Senkevich
2015-05-27 12:13 ` H.J. Lu
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