From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by sourceware.org (Postfix) with ESMTPS id F3D1E3858C60 for ; Tue, 7 Dec 2021 12:54:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F3D1E3858C60 Received: by mail-pj1-x1034.google.com with SMTP id w33-20020a17090a6ba400b001a722a06212so1997548pjj.0 for ; Tue, 07 Dec 2021 04:54:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=cg8oYlzTGgJCdLC1gXcDb6uKCghNkUNWEae9jSl1IX4=; b=4lDnPd+TOBrSHMUfe1Mxyie3dKpHQ3uoXhZoNvYd/VYkEjKU4Qqf1Tv4vTNMK08fwV RMKbfVeU0VM2jiLqjlWf4FTunTQJG9yXfYUeVkwEST4ovctzOxfmhwG/tDoxaNY70Ip9 ejksgmeWUCbb7fwSKW4DkfdcylCUZxe1TTS/O2eEP8BGZ7p8fOGCOet2Efc6H75YXxOU nvCa1II+/0Aa4HDZZ+EtanBhEfYuOGMeN/N89dCNh4alC5zitKIsQNQeSj43Ht74m+Td JkGW643CewFvW+7+Q8TghrGX0ig2ioolZ1BsRztrFw2EYgc46/UCSge6N52tfIxhzda1 07mw== X-Gm-Message-State: AOAM532Qp8Z/Hb3dejZRMLnR7DqBWLZ7SRbp6LH8DQV3F6RhnGltasHq wrX10CPzgQjq9sq7niFzcieaCgbhgPoRhMNGJMg= X-Google-Smtp-Source: ABdhPJyE/Ms8NnOyZnLWIjEDj+ON5utp+FXnyGYAGQJYlzI0mO2xv7TLrz1meBriXC5ob8gsF3WcsB+PgEVzkVdq+as= X-Received: by 2002:a17:90b:1e0e:: with SMTP id pg14mr6310589pjb.143.1638881673075; Tue, 07 Dec 2021 04:54:33 -0800 (PST) MIME-Version: 1.0 References: <20211206032303.7159-1-hjl.tools@gmail.com> In-Reply-To: From: "H.J. Lu" Date: Tue, 7 Dec 2021 04:53:57 -0800 Message-ID: Subject: Re: [PATCH] x86: Don't set Prefer_No_AVX512 for processors with AVX512 and AVX-VNNI To: Noah Goldstein , Thiago Macieira , Arjan van de Ven Cc: GNU C Library Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3028.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Dec 2021 12:54:35 -0000 On Mon, Dec 6, 2021 at 11:47 PM Noah Goldstein wrote: > > On Sun, Dec 5, 2021 at 9:23 PM H.J. Lu via Libc-alpha > wrote: > > > > Don't set Prefer_No_AVX512 on processors with AVX512 and AVX-VNNI since > > they won't lower CPU frequency when ZMM load and store instructions are > > used. > > --- > > sysdeps/x86/cpu-features.c | 7 +++++-- > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > > index be2498b2e7..311ade1f26 100644 > > --- a/sysdeps/x86/cpu-features.c > > +++ b/sysdeps/x86/cpu-features.c > > @@ -538,8 +538,11 @@ init_cpu_features (struct cpu_features *cpu_features) > > |= bit_arch_Prefer_No_VZEROUPPER; > > else > > { > > - cpu_features->preferred[index_arch_Prefer_No_AVX512] > > - |= bit_arch_Prefer_No_AVX512; > > + /* Processors with AVX512 and AVX-VNNI won't lower CPU frequency > > + when ZMM load and store instructions are used. */ > > + if (!CPU_FEATURES_CPU_P (cpu_features, AVX_VNNI)) > > + cpu_features->preferred[index_arch_Prefer_No_AVX512] > > + |= bit_arch_Prefer_No_AVX512; > > > > /* Avoid RTM abort triggered by VZEROUPPER inside a > > transactionally executing RTM region. */ > > -- > > 2.33.1 > > > > Should we also do Rocket Lake? > According to Travis Downs at least downclocking is an issue there ether: > https://travisdowns.github.io/blog/2020/08/19/icl-avx512-freq.html#rocket-lake Thiago, Arjan, Is this true that Rocket Lake can use ZMM load/store? -- H.J.