* [PATCH] x86-64: Don't use SSE resolvers for ISA level 3 or above
@ 2024-02-28 17:51 H.J. Lu
2024-02-28 17:57 ` Noah Goldstein
2024-02-29 20:55 ` Richard Henderson
0 siblings, 2 replies; 8+ messages in thread
From: H.J. Lu @ 2024-02-28 17:51 UTC (permalink / raw)
To: libc-alpha; +Cc: goldstein.w.n, skpgkp2
When glibc is built with ISA level 3 or above enabled, SSE resolvers
aren't available and glibc fails to build:
ld: .../elf/librtld.os: in function `init_cpu_features':
.../elf/../sysdeps/x86/cpu-features.c:1200:(.text+0x1445f): undefined reference to `_dl_runtime_resolve_fxsave'
ld: .../elf/librtld.os: relocation R_X86_64_PC32 against undefined hidden symbol `_dl_runtime_resolve_fxsave' can not be used when making a shared object
/usr/local/bin/ld: final link failed: bad value
For ISA level 3 or above, don't use _dl_runtime_resolve_fxsave nor
_dl_tlsdesc_dynamic_fxsave and also exclude _dl_tlsdesc_dynamic_fxsave.
This fixes BZ #31429.
---
sysdeps/x86/cpu-features.c | 17 +++++++++++------
sysdeps/x86_64/dl-tlsdesc.S | 15 +++++++++------
2 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index d71e8d3d2e..e7c7ece462 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -18,6 +18,7 @@
#include <dl-hwcap.h>
#include <libc-pointer-arith.h>
+#include <isa-level.h>
#include <get-isa-level.h>
#include <cacheinfo.h>
#include <dl-cacheinfo.h>
@@ -1195,7 +1196,9 @@ no_cpuid:
TUNABLE_CALLBACK (set_x86_shstk));
#endif
+#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
+#endif
{
if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC))
{
@@ -1216,22 +1219,24 @@ no_cpuid:
#endif
}
}
+#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
else
{
-#ifdef __x86_64__
+# ifdef __x86_64__
GLRO(dl_x86_64_runtime_resolve) = _dl_runtime_resolve_fxsave;
-# ifdef SHARED
+# ifdef SHARED
GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave;
-# endif
-#else
-# ifdef SHARED
+# endif
+# else
+# ifdef SHARED
if (CPU_FEATURE_USABLE_P (cpu_features, FXSR))
GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave;
else
GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fnsave;
+# endif
# endif
-#endif
}
+#endif
#ifdef SHARED
# ifdef __x86_64__
diff --git a/sysdeps/x86_64/dl-tlsdesc.S b/sysdeps/x86_64/dl-tlsdesc.S
index ea69f5223a..057a10862a 100644
--- a/sysdeps/x86_64/dl-tlsdesc.S
+++ b/sysdeps/x86_64/dl-tlsdesc.S
@@ -20,6 +20,7 @@
#include <tls.h>
#include <cpu-features-offsets.h>
#include <features-offsets.h>
+#include <isa-level.h>
#include "tlsdesc.h"
#include "dl-trampoline-save.h"
@@ -79,12 +80,14 @@ _dl_tlsdesc_undefweak:
.size _dl_tlsdesc_undefweak, .-_dl_tlsdesc_undefweak
#ifdef SHARED
-# define USE_FXSAVE
-# define STATE_SAVE_ALIGNMENT 16
-# define _dl_tlsdesc_dynamic _dl_tlsdesc_dynamic_fxsave
-# include "dl-tlsdesc-dynamic.h"
-# undef _dl_tlsdesc_dynamic
-# undef USE_FXSAVE
+# if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
+# define USE_FXSAVE
+# define STATE_SAVE_ALIGNMENT 16
+# define _dl_tlsdesc_dynamic _dl_tlsdesc_dynamic_fxsave
+# include "dl-tlsdesc-dynamic.h"
+# undef _dl_tlsdesc_dynamic
+# undef USE_FXSAVE
+# endif
# define USE_XSAVE
# define STATE_SAVE_ALIGNMENT 64
--
2.43.2
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86-64: Don't use SSE resolvers for ISA level 3 or above
2024-02-28 17:51 [PATCH] x86-64: Don't use SSE resolvers for ISA level 3 or above H.J. Lu
@ 2024-02-28 17:57 ` Noah Goldstein
2024-02-29 20:55 ` Richard Henderson
1 sibling, 0 replies; 8+ messages in thread
From: Noah Goldstein @ 2024-02-28 17:57 UTC (permalink / raw)
To: H.J. Lu; +Cc: libc-alpha, skpgkp2
On Wed, Feb 28, 2024 at 11:51 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> When glibc is built with ISA level 3 or above enabled, SSE resolvers
> aren't available and glibc fails to build:
>
> ld: .../elf/librtld.os: in function `init_cpu_features':
> .../elf/../sysdeps/x86/cpu-features.c:1200:(.text+0x1445f): undefined reference to `_dl_runtime_resolve_fxsave'
> ld: .../elf/librtld.os: relocation R_X86_64_PC32 against undefined hidden symbol `_dl_runtime_resolve_fxsave' can not be used when making a shared object
> /usr/local/bin/ld: final link failed: bad value
>
> For ISA level 3 or above, don't use _dl_runtime_resolve_fxsave nor
> _dl_tlsdesc_dynamic_fxsave and also exclude _dl_tlsdesc_dynamic_fxsave.
>
> This fixes BZ #31429.
> ---
> sysdeps/x86/cpu-features.c | 17 +++++++++++------
> sysdeps/x86_64/dl-tlsdesc.S | 15 +++++++++------
> 2 files changed, 20 insertions(+), 12 deletions(-)
>
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index d71e8d3d2e..e7c7ece462 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -18,6 +18,7 @@
>
> #include <dl-hwcap.h>
> #include <libc-pointer-arith.h>
> +#include <isa-level.h>
> #include <get-isa-level.h>
> #include <cacheinfo.h>
> #include <dl-cacheinfo.h>
> @@ -1195,7 +1196,9 @@ no_cpuid:
> TUNABLE_CALLBACK (set_x86_shstk));
> #endif
>
> +#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
> if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
> +#endif
> {
> if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC))
> {
> @@ -1216,22 +1219,24 @@ no_cpuid:
> #endif
> }
> }
> +#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
> else
> {
> -#ifdef __x86_64__
> +# ifdef __x86_64__
> GLRO(dl_x86_64_runtime_resolve) = _dl_runtime_resolve_fxsave;
> -# ifdef SHARED
> +# ifdef SHARED
> GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave;
> -# endif
> -#else
> -# ifdef SHARED
> +# endif
> +# else
> +# ifdef SHARED
> if (CPU_FEATURE_USABLE_P (cpu_features, FXSR))
> GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave;
> else
> GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fnsave;
> +# endif
> # endif
> -#endif
> }
> +#endif
>
> #ifdef SHARED
> # ifdef __x86_64__
> diff --git a/sysdeps/x86_64/dl-tlsdesc.S b/sysdeps/x86_64/dl-tlsdesc.S
> index ea69f5223a..057a10862a 100644
> --- a/sysdeps/x86_64/dl-tlsdesc.S
> +++ b/sysdeps/x86_64/dl-tlsdesc.S
> @@ -20,6 +20,7 @@
> #include <tls.h>
> #include <cpu-features-offsets.h>
> #include <features-offsets.h>
> +#include <isa-level.h>
> #include "tlsdesc.h"
> #include "dl-trampoline-save.h"
>
> @@ -79,12 +80,14 @@ _dl_tlsdesc_undefweak:
> .size _dl_tlsdesc_undefweak, .-_dl_tlsdesc_undefweak
>
> #ifdef SHARED
> -# define USE_FXSAVE
> -# define STATE_SAVE_ALIGNMENT 16
> -# define _dl_tlsdesc_dynamic _dl_tlsdesc_dynamic_fxsave
> -# include "dl-tlsdesc-dynamic.h"
> -# undef _dl_tlsdesc_dynamic
> -# undef USE_FXSAVE
> +# if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
> +# define USE_FXSAVE
> +# define STATE_SAVE_ALIGNMENT 16
> +# define _dl_tlsdesc_dynamic _dl_tlsdesc_dynamic_fxsave
> +# include "dl-tlsdesc-dynamic.h"
> +# undef _dl_tlsdesc_dynamic
> +# undef USE_FXSAVE
> +# endif
>
> # define USE_XSAVE
> # define STATE_SAVE_ALIGNMENT 64
> --
> 2.43.2
>
LGTM.
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86-64: Don't use SSE resolvers for ISA level 3 or above
2024-02-28 17:51 [PATCH] x86-64: Don't use SSE resolvers for ISA level 3 or above H.J. Lu
2024-02-28 17:57 ` Noah Goldstein
@ 2024-02-29 20:55 ` Richard Henderson
2024-03-01 2:40 ` Sunil Pandey
1 sibling, 1 reply; 8+ messages in thread
From: Richard Henderson @ 2024-02-29 20:55 UTC (permalink / raw)
To: H.J. Lu, libc-alpha; +Cc: goldstein.w.n, skpgkp2
On 2/28/24 07:51, H.J. Lu wrote:
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -18,6 +18,7 @@
>
> #include <dl-hwcap.h>
> #include <libc-pointer-arith.h>
> +#include <isa-level.h>
> #include <get-isa-level.h>
> #include <cacheinfo.h>
> #include <dl-cacheinfo.h>
> @@ -1195,7 +1196,9 @@ no_cpuid:
> TUNABLE_CALLBACK (set_x86_shstk));
> #endif
>
> +#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
> if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
> +#endif
> {
> if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC))
> {
Surely this can be written with IF and not IFDEF:
if (MINIMUM_X86_ISA_LEVEL >= AVX_X86_ISA_LEVEL
|| GLRO(dl_x86_cpu_features).xsave_state_size != 0)
r~
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86-64: Don't use SSE resolvers for ISA level 3 or above
2024-02-29 20:55 ` Richard Henderson
@ 2024-03-01 2:40 ` Sunil Pandey
2024-03-01 22:22 ` Richard Henderson
0 siblings, 1 reply; 8+ messages in thread
From: Sunil Pandey @ 2024-03-01 2:40 UTC (permalink / raw)
To: Richard Henderson; +Cc: H.J. Lu, libc-alpha, goldstein.w.n
[-- Attachment #1: Type: text/plain, Size: 1252 bytes --]
On Thu, Feb 29, 2024 at 12:55 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 2/28/24 07:51, H.J. Lu wrote:
> > --- a/sysdeps/x86/cpu-features.c
> > +++ b/sysdeps/x86/cpu-features.c
> > @@ -18,6 +18,7 @@
> >
> > #include <dl-hwcap.h>
> > #include <libc-pointer-arith.h>
> > +#include <isa-level.h>
> > #include <get-isa-level.h>
> > #include <cacheinfo.h>
> > #include <dl-cacheinfo.h>
> > @@ -1195,7 +1196,9 @@ no_cpuid:
> > TUNABLE_CALLBACK (set_x86_shstk));
> > #endif
> >
> > +#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
> > if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
> > +#endif
> > {
> > if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC))
> > {
>
> Surely this can be written with IF and not IFDEF:
>
> if (MINIMUM_X86_ISA_LEVEL >= AVX_X86_ISA_LEVEL
> || GLRO(dl_x86_cpu_features).xsave_state_size != 0)
>
For sure it can be written like IF, but using IFDEF has the following perf
and code size advantage.
For MINIMUM_X86_ISA_LEVEL >= AVX_X86_ISA_LEVEL case
it will remove conditional
if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
and else block code of this conditional during preprocessing.
--Sunil
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86-64: Don't use SSE resolvers for ISA level 3 or above
2024-03-01 2:40 ` Sunil Pandey
@ 2024-03-01 22:22 ` Richard Henderson
2024-03-02 0:18 ` Sunil Pandey
0 siblings, 1 reply; 8+ messages in thread
From: Richard Henderson @ 2024-03-01 22:22 UTC (permalink / raw)
To: Sunil Pandey; +Cc: H.J. Lu, libc-alpha, goldstein.w.n
On 2/29/24 16:40, Sunil Pandey wrote:
>
>
> On Thu, Feb 29, 2024 at 12:55 PM Richard Henderson <richard.henderson@linaro.org
> <mailto:richard.henderson@linaro.org>> wrote:
>
> On 2/28/24 07:51, H.J. Lu wrote:
> > --- a/sysdeps/x86/cpu-features.c
> > +++ b/sysdeps/x86/cpu-features.c
> > @@ -18,6 +18,7 @@
> >
> > #include <dl-hwcap.h>
> > #include <libc-pointer-arith.h>
> > +#include <isa-level.h>
> > #include <get-isa-level.h>
> > #include <cacheinfo.h>
> > #include <dl-cacheinfo.h>
> > @@ -1195,7 +1196,9 @@ no_cpuid:
> > TUNABLE_CALLBACK (set_x86_shstk));
> > #endif
> >
> > +#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
> > if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
> > +#endif
> > {
> > if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC))
> > {
>
> Surely this can be written with IF and not IFDEF:
>
> if (MINIMUM_X86_ISA_LEVEL >= AVX_X86_ISA_LEVEL
> || GLRO(dl_x86_cpu_features).xsave_state_size != 0)
>
>
> For sure it can be written like IF, but using IFDEF has the following perf and code size
> advantage.
>
> For MINIMUM_X86_ISA_LEVEL >= AVX_X86_ISA_LEVEL case
>
> it will remove conditional
>
> if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
>
> and else block code of this conditional during preprocessing.
You miss the point -- both of these are constants and will be folded by the compiler.
There is no perf or code size advantage for cpp.
r~
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86-64: Don't use SSE resolvers for ISA level 3 or above
2024-03-01 22:22 ` Richard Henderson
@ 2024-03-02 0:18 ` Sunil Pandey
2024-03-02 0:38 ` [PATCH] x86-64: Simplify minimum ISA check ifdef conditional with if Sunil K Pandey
0 siblings, 1 reply; 8+ messages in thread
From: Sunil Pandey @ 2024-03-02 0:18 UTC (permalink / raw)
To: Richard Henderson; +Cc: H.J. Lu, libc-alpha, goldstein.w.n
[-- Attachment #1: Type: text/plain, Size: 1856 bytes --]
On Fri, Mar 1, 2024 at 2:23 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 2/29/24 16:40, Sunil Pandey wrote:
> >
> >
> > On Thu, Feb 29, 2024 at 12:55 PM Richard Henderson <
> richard.henderson@linaro.org
> > <mailto:richard.henderson@linaro.org>> wrote:
> >
> > On 2/28/24 07:51, H.J. Lu wrote:
> > > --- a/sysdeps/x86/cpu-features.c
> > > +++ b/sysdeps/x86/cpu-features.c
> > > @@ -18,6 +18,7 @@
> > >
> > > #include <dl-hwcap.h>
> > > #include <libc-pointer-arith.h>
> > > +#include <isa-level.h>
> > > #include <get-isa-level.h>
> > > #include <cacheinfo.h>
> > > #include <dl-cacheinfo.h>
> > > @@ -1195,7 +1196,9 @@ no_cpuid:
> > > TUNABLE_CALLBACK (set_x86_shstk));
> > > #endif
> > >
> > > +#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
> > > if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
> > > +#endif
> > > {
> > > if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC))
> > > {
> >
> > Surely this can be written with IF and not IFDEF:
> >
> > if (MINIMUM_X86_ISA_LEVEL >= AVX_X86_ISA_LEVEL
> > || GLRO(dl_x86_cpu_features).xsave_state_size != 0)
> >
> >
> > For sure it can be written like IF, but using IFDEF has the following
> perf and code size
> > advantage.
> >
> > For MINIMUM_X86_ISA_LEVEL >= AVX_X86_ISA_LEVEL case
> >
> > it will remove conditional
> >
> > if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
> >
> > and else block code of this conditional during preprocessing.
>
> You miss the point -- both of these are constants and will be folded by
> the compiler.
> There is no perf or code size advantage for cpp.
>
>
Got it. Will submit a patch to fix it.
--Sunil
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] x86-64: Simplify minimum ISA check ifdef conditional with if
2024-03-02 0:18 ` Sunil Pandey
@ 2024-03-02 0:38 ` Sunil K Pandey
2024-03-03 21:46 ` H.J. Lu
0 siblings, 1 reply; 8+ messages in thread
From: Sunil K Pandey @ 2024-03-02 0:38 UTC (permalink / raw)
To: libc-alpha
Replace minimum ISA check ifdef conditional with if. Since
MINIMUM_X86_ISA_LEVEL and AVX_X86_ISA_LEVEL are compile time constants,
compiler will perform constant folding optimization getting same result.
---
sysdeps/x86/cpu-features.c | 19 ++++++++-----------
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index e7c7ece462..4ea373dffa 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -1196,9 +1196,8 @@ no_cpuid:
TUNABLE_CALLBACK (set_x86_shstk));
#endif
-#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
- if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
-#endif
+ if (MINIMUM_X86_ISA_LEVEL >= AVX_X86_ISA_LEVEL
+ || (GLRO(dl_x86_cpu_features).xsave_state_size != 0))
{
if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC))
{
@@ -1219,24 +1218,22 @@ no_cpuid:
#endif
}
}
-#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
else
{
-# ifdef __x86_64__
+#ifdef __x86_64__
GLRO(dl_x86_64_runtime_resolve) = _dl_runtime_resolve_fxsave;
-# ifdef SHARED
+# ifdef SHARED
GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave;
-# endif
-# else
-# ifdef SHARED
+# endif
+#else
+# ifdef SHARED
if (CPU_FEATURE_USABLE_P (cpu_features, FXSR))
GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave;
else
GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fnsave;
-# endif
# endif
- }
#endif
+ }
#ifdef SHARED
# ifdef __x86_64__
--
2.43.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] x86-64: Simplify minimum ISA check ifdef conditional with if
2024-03-02 0:38 ` [PATCH] x86-64: Simplify minimum ISA check ifdef conditional with if Sunil K Pandey
@ 2024-03-03 21:46 ` H.J. Lu
0 siblings, 0 replies; 8+ messages in thread
From: H.J. Lu @ 2024-03-03 21:46 UTC (permalink / raw)
To: Sunil K Pandey; +Cc: libc-alpha
On Fri, Mar 1, 2024 at 4:40 PM Sunil K Pandey <skpgkp2@gmail.com> wrote:
>
> Replace minimum ISA check ifdef conditional with if. Since
> MINIMUM_X86_ISA_LEVEL and AVX_X86_ISA_LEVEL are compile time constants,
> compiler will perform constant folding optimization getting same result.
> ---
> sysdeps/x86/cpu-features.c | 19 ++++++++-----------
> 1 file changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index e7c7ece462..4ea373dffa 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -1196,9 +1196,8 @@ no_cpuid:
> TUNABLE_CALLBACK (set_x86_shstk));
> #endif
>
> -#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
> - if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
> -#endif
> + if (MINIMUM_X86_ISA_LEVEL >= AVX_X86_ISA_LEVEL
> + || (GLRO(dl_x86_cpu_features).xsave_state_size != 0))
> {
> if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC))
> {
> @@ -1219,24 +1218,22 @@ no_cpuid:
> #endif
> }
> }
> -#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
> else
> {
> -# ifdef __x86_64__
> +#ifdef __x86_64__
> GLRO(dl_x86_64_runtime_resolve) = _dl_runtime_resolve_fxsave;
> -# ifdef SHARED
> +# ifdef SHARED
> GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave;
> -# endif
> -# else
> -# ifdef SHARED
> +# endif
> +#else
> +# ifdef SHARED
> if (CPU_FEATURE_USABLE_P (cpu_features, FXSR))
> GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave;
> else
> GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fnsave;
> -# endif
> # endif
> - }
> #endif
> + }
>
> #ifdef SHARED
> # ifdef __x86_64__
> --
> 2.43.0
>
LGTM.
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-03-03 21:46 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-02-28 17:51 [PATCH] x86-64: Don't use SSE resolvers for ISA level 3 or above H.J. Lu
2024-02-28 17:57 ` Noah Goldstein
2024-02-29 20:55 ` Richard Henderson
2024-03-01 2:40 ` Sunil Pandey
2024-03-01 22:22 ` Richard Henderson
2024-03-02 0:18 ` Sunil Pandey
2024-03-02 0:38 ` [PATCH] x86-64: Simplify minimum ISA check ifdef conditional with if Sunil K Pandey
2024-03-03 21:46 ` H.J. Lu
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