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From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 4 Nov 2021 07:31:03 -0700
Message-ID: <CAMe9rOrW8AwqnNbNMp53BL3XsKfgaeYzivVTTH8FQbSavJGqgw@mail.gmail.com>
Subject: Re: [PATCH] x86: Optimize atomic_compare_and_exchange_[val|bool]_acq
 [BZ #28537]
To: Florian Weimer <fweimer@redhat.com>, liuhongt <hongtao.liu@intel.com>, 
 Hongyu Wang <hongyu.wang@intel.com>
Cc: "H.J. Lu via Libc-alpha" <libc-alpha@sourceware.org>
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On Thu, Nov 4, 2021 at 3:15 AM Florian Weimer <fweimer@redhat.com> wrote:
>
> * H. J. Lu:
>
> >> Shouldn't GCC be fixed to generate the appropriate instruction sequence
> >> for this architecture?  Should we perhaps switch to compiler atomics for
> >> x86 instead of defining our own?
> >
> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103065
> >
> > In the meantime, we should help older compilers.
>
> But wouldn't that extra read persist with fixed compilers, due to the
> memory barrier?  So that there are two reads?

Yes, this could be a problem.

> Maybe we need a hint flag for __atomic_compare_exchange_n, encoded in
> the memory order?

We need a way to identify the fixed compiler.  We can add a predefined macro,
something like __GCC_HAVE_SYNC_COMPARE_AND_SWAP_LOAD_CHECK.

-- 
H.J.