From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by sourceware.org (Postfix) with ESMTPS id 5E7C2387057C for ; Wed, 14 Dec 2022 21:36:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5E7C2387057C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-lj1-x236.google.com with SMTP id s10so8058674ljg.1 for ; Wed, 14 Dec 2022 13:36:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=hu4PCF94M9ByJyWqxhgLRtJj46mHCyJwLfMOMiP7JT0=; b=kkA7/gSdlLL8NnD4scT44ogljxVUquUwucVpb5ikv6yyLR9LGuKTJmYmZdCwhc53YA mNpGRBlZKVfTJDHfrhQFCYQpBD3SbcC9d5D8zo0ouwafwKEn4ta9Hg+GJ4O1S+KwdG69 PRVagZ5YBOFwByyP5/15GKUTYrml7nXogk9Jbc5bh1zOYNmkrGCRgJBBy4BUkjg70DOD XPjcur4k+nemBTxNRq2bnFp5Pz7p+klRmGlqxiZ5PfbrF2sn5iltgPRB9ZEnMkVaqUQ4 fueTuiStGdWxuJ6gNNhfStm1W/KwXd4dF7PgwUlKEKo55CgjguZDUZj7EBf+Pv5BhUi1 6eWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=hu4PCF94M9ByJyWqxhgLRtJj46mHCyJwLfMOMiP7JT0=; b=BRh9GeWk4/QjR9D66k26WtnEsmvnQSN7lcahxV87MjL0A+74VR5VYkCLOLJgT2jMTB MgaRI8VZLiWhcEHLbb7C0GxdcjVvICS6WoiQz1ztk4r/v6t0u/roLdRYru856DABmctA h0KtoNUnW3ShtPeueGNk2iPEPpjRTVSaAk/jtGb4EHyEoht/jKzbTArE3feyBaX3c0mA U+KWS0ICbhWV/0ePzGeIn1EYuJYuPMEhQw6s5Mw6VqalMa08zY0lD6mh94/bz5UEcBoQ Uu2oLkh3zm8RQfys1mH8a1pCCCKfEYNTmCqC3mNIAJZjCyR0vffiE2/W7R948GPijqAQ LSVg== X-Gm-Message-State: ANoB5pmHrLXQa3w+Tlg/ynxTK3yCsret/ZV4oohxpkvNp/e3a0IYycdH c3VbSudyLcz06pcsA5f6kh+jhqABmCPpBL4d94M= X-Google-Smtp-Source: AA0mqf5cuIu3/+Iho0lGROn697hCPLLBevjpyzYkM5mXhhpFnXxE3Jizi9H7uZMwegTqe2JwLxfi9c2ezF8lPsMWxr0= X-Received: by 2002:a05:651c:247:b0:278:fa62:bc91 with SMTP id x7-20020a05651c024700b00278fa62bc91mr29120967ljn.100.1671053787765; Wed, 14 Dec 2022 13:36:27 -0800 (PST) MIME-Version: 1.0 References: <20221214001147.2814047-1-goldstein.w.n@gmail.com> <20221214185210.2930992-1-goldstein.w.n@gmail.com> In-Reply-To: <20221214185210.2930992-1-goldstein.w.n@gmail.com> From: "H.J. Lu" Date: Wed, 14 Dec 2022 13:35:49 -0800 Message-ID: Subject: Re: [PATCH v4] x86: Prevent SIGSEGV in memcmp-sse2 when data is concurrently modified [BZ #29863] To: Noah Goldstein Cc: libc-alpha@sourceware.org, carlos@systemhalted.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3022.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Dec 14, 2022 at 10:52 AM Noah Goldstein wrote: > > In the case of INCORRECT usage of `memcmp(a, b, N)` where `a` and `b` > are concurrently modified as `memcmp` runs, there can be a SIGSEGV > in `L(ret_nonzero_vec_end_0)` because the sequential logic > assumes that `(rdx - 32 + rax)` is a positive 32-bit integer. > > To be clear, this change does not mean the usage of `memcmp` is > supported. The program behaviour is undefined (UB) in the > presence of data races, and `memcmp` is incorrect when the values > of `a` and/or `b` are modified concurrently (data race). This UB > may manifest itself as a SIGSEGV. That being said, if we can > allow the idiomatic use cases, like those in yottadb with > opportunistic concurrency control (OCC), to execute without a > SIGSEGV, at no cost to regular use cases, then we can aim to > minimize harm to those existing users. > > The fix replaces a 32-bit `addl %edx, %eax` with the 64-bit variant > `addq %rdx, %rax`. The 1-extra byte of code size from using the > 64-bit instruction doesn't contribute to overall code size as the > next target is aligned and has multiple bytes of `nop` padding > before it. As well all the logic between the add and `ret` still > fits in the same fetch block, so the cost of this change is > basically zero. > > The relevant sequential logic can be seen in the following > pseudo-code: > ``` > /* > * rsi = a > * rdi = b > * rdx = len - 32 > */ > /* cmp a[0:15] and b[0:15]. Since length is known to be [17, 32] > in this case, this check is also assumed to cover a[0:(31 - len)] > and b[0:(31 - len)]. */ > movups (%rsi), %xmm0 > movups (%rdi), %xmm1 > PCMPEQ %xmm0, %xmm1 > pmovmskb %xmm1, %eax > subl %ecx, %eax > jnz L(END_NEQ) > > /* cmp a[len-16:len-1] and b[len-16:len-1]. */ > movups 16(%rsi, %rdx), %xmm0 > movups 16(%rdi, %rdx), %xmm1 > PCMPEQ %xmm0, %xmm1 > pmovmskb %xmm1, %eax > subl %ecx, %eax > jnz L(END_NEQ2) > ret > > L(END2): > /* Position first mismatch. */ > bsfl %eax, %eax > > /* The sequential version is able to assume this value is a > positive 32-bit value because the first check included bytes in > range a[0:(31 - len)] and b[0:(31 - len)] so `eax` must be > greater than `31 - len` so the minimum value of `edx` + `eax` is > `(len - 32) + (32 - len) >= 0`. In the concurrent case, however, > `a` or `b` could have been changed so a mismatch in `eax` less or > equal than `(31 - len)` is possible (the new low bound is `(16 - > len)`. This can result in a negative 32-bit signed integer, which > when zero extended to 64-bits is a random large value this out > out of bounds. */ > addl %edx, %eax > > /* Crash here because 32-bit negative number in `eax` zero > extends to out of bounds 64-bit offset. */ > movzbl 16(%rdi, %rax), %ecx > movzbl 16(%rsi, %rax), %eax > ``` > > This fix is quite simple, just make the `addl %edx, %eax` 64 bit (i.e > `addq %rdx, %rax`). This prevents the 32-bit zero extension > and since `eax` is still a low bound of `16 - len` the `rdx + rax` > is bound by `(len - 32) - (16 - len) >= -16`. Since we have a > fixed offset of `16` in the memory access this must be in bounds. > --- > sysdeps/x86_64/multiarch/memcmp-sse2.S | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/sysdeps/x86_64/multiarch/memcmp-sse2.S b/sysdeps/x86_64/multiarch/memcmp-sse2.S > index afd450d020..51bc9344f0 100644 > --- a/sysdeps/x86_64/multiarch/memcmp-sse2.S > +++ b/sysdeps/x86_64/multiarch/memcmp-sse2.S > @@ -308,7 +308,17 @@ L(ret_nonzero_vec_end_0): > setg %dl > leal -1(%rdx, %rdx), %eax > # else > - addl %edx, %eax > + /* Use `addq` instead of `addl` here so that even if `rax` + `rdx` > + is negative value of the sum will be usable as a 64-bit offset > + (negative 32-bit numbers zero-extend to a large and often > + out-of-bounds 64-bit offsets). Note that `rax` + `rdx` >= 0 is > + an invariant when `memcmp` is used correctly, but if the input > + strings `rsi`/`rdi` are concurrently modified as the function > + runs (there is a Data-Race) it is possible for `rax` + `rdx` to > + be negative. Given that there is virtually no extra to cost > + using `addq` instead of `addl` we may as well protect the > + data-race case. */ > + addq %rdx, %rax > movzbl (VEC_SIZE * -1 + SIZE_OFFSET)(%rsi, %rax), %ecx > movzbl (VEC_SIZE * -1 + SIZE_OFFSET)(%rdi, %rax), %eax > subl %ecx, %eax > -- > 2.34.1 > LGTM. Thanks. -- H.J.