From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by sourceware.org (Postfix) with ESMTPS id 721653857827 for ; Tue, 28 Jun 2022 02:39:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 721653857827 Received: by mail-pj1-x102d.google.com with SMTP id dw10-20020a17090b094a00b001ed00a16eb4so11256272pjb.2 for ; Mon, 27 Jun 2022 19:39:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+GfLuXU5UPOoeQ1uUDhgaGI35Tto+qcOWE8lAZTB7iU=; b=lMTQpIsO0AMIAhpx5c2QN1afg6A9NgunP6QKbR50Q++Fpt8ymTZMcPP8/01XD25mLC 2BuvNpdwYUikapHGUJobxvhTkewIL6+U6RmAfX8nfjTL+kx9ZX4OtyPKB75/mfa6p8le voOjAPSxBVnhBvUVAfGtncNd9FWpTQV5Nce8IliAWmQKcYCnwOqb1Y9smITFAu0HGH72 btLOw8aFso53dZVo0Dh4p9RDCoXq3mQwnYJpW3YEw55QirN6mmhdBJ36WzRkU9Ja4AHw wub6CciYO+XDCmpJfj2oEOccfyjtt4fm2o3VMACiVYXSMWnhBVFmpBLjaxqjW0jwI1ER SQNw== X-Gm-Message-State: AJIora/5nIyqCTkvkITcLRmtbEffSMqm0gUMqj9QKU7WmVctgVIMZfxn kCF2s6P8onZ/mw5GMMf7xzTSCKc1blpKQfNF4+I= X-Google-Smtp-Source: AGRyM1vUajg6hlGW3w8Rgn0brLj8F3ki7ubDlKuynvvBxljXzlvUyo/Ic3wH2Jwtgo3MFfnlF3O0ZvwKbiaZ2QWy7u8= X-Received: by 2002:a17:902:a502:b0:15e:c251:b769 with SMTP id s2-20020a170902a50200b0015ec251b769mr1321774plq.115.1656383951518; Mon, 27 Jun 2022 19:39:11 -0700 (PDT) MIME-Version: 1.0 References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> <20220628020342.213807-1-goldstein.w.n@gmail.com> In-Reply-To: From: "H.J. Lu" Date: Mon, 27 Jun 2022 19:38:35 -0700 Message-ID: Subject: Re: [PATCH v2] x86: Add more feature definitions to isa-level.h To: Noah Goldstein Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3024.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 02:39:13 -0000 On Mon, Jun 27, 2022 at 7:34 PM Noah Goldstein wrote: > > On Mon, Jun 27, 2022 at 7:30 PM H.J. Lu wrote: > > > > On Mon, Jun 27, 2022 at 7:03 PM Noah Goldstein wrote: > > > > > > This commit doesn't change anything in itself. It is just to add > > > definitions that will be needed by future patches. > > > --- > > > sysdeps/x86/isa-level.h | 10 ++++++++++ > > > 1 file changed, 10 insertions(+) > > > > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h > > > index f293aea906..024d1deb80 100644 > > > --- a/sysdeps/x86/isa-level.h > > > +++ b/sysdeps/x86/isa-level.h > > > @@ -71,11 +71,13 @@ > > > #define AVX512F_X86_ISA_LEVEL 4 > > > #define AVX512VL_X86_ISA_LEVEL 4 > > > #define AVX512BW_X86_ISA_LEVEL 4 > > > +#define AVX512DQ_X86_ISA_LEVEL 4 > > > > > > /* ISA level >= 3 guaranteed includes. */ > > > #define AVX_X86_ISA_LEVEL 3 > > > #define AVX2_X86_ISA_LEVEL 3 > > > #define BMI2_X86_ISA_LEVEL 3 > > > +#define MOVBE_X86_ISA_LEVEL 3 > > > > > > /* NB: This feature is enabled when ISA level >= 3, which was disabled > > > for the following CPUs: > > > @@ -89,6 +91,14 @@ > > > when ISA level < 3. */ > > > #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 > > > > > > +/* ISA level >= 2 guaranteed includes. */ > > Have a comment for ISA level 2 here. ISA is included. But arch features can be enabled/disabled. > > > +#define SSE4_2_X86_ISA_LEVEL 2 > > > +#define SSSE3_X86_ISA_LEVEL 2 > > > + > > > +/* NB: This feature is enabled when ISA level >= 2. No CPUs should be > > > + affected by this. */ > > > > /* Features enabled when ISA level >= 2. */ > > Hm? This is singular. Will more be added? > > > > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 > > > + > > > /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P > > > macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P > > > runtime checks. They differ in two ways. > > > -- > > > 2.34.1 > > > > > > > > > -- > > H.J. -- H.J.