From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 55809 invoked by alias); 31 May 2017 19:48:49 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Received: (qmail 48996 invoked by uid 89); 31 May 2017 19:48:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.1 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=ham version=3.3.2 spammy=reserved, family X-HELO: mail-qk0-f193.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to; bh=6Y/0MpiJSkucpmaTd1uqWS5kxbEZ25o8IMej5Uzn4KQ=; b=ovd/Har8JlYYPhZ6+Z8LECjVfN7HOq1Udo7zHGdJYtaF5PAtD7LgzrUBX0idK/y3d1 vnhagsOd2U//6kAa/4s46lR3wMjc4PxufDvs4gyIH+tv4SBc3znmmTsCzjAFi4VtylPt lrLLAfOzGhx8iWsFpPHp9Rf0GazwdFWhegt0TKcXMq8VGS+w9aozx3Zn3+xYujaIa2aX uNe1LwvPrv6JDZMdz1T8rxv2bdBWnr2vpQe++ckjXFA00suunEwZg1P0XFN6+uOOW2fE InsBl+kQE3eX/cACiOBjr1BWzEdV42oy9d8Z2dgYzLYDL8mOFGr2XbGGoIkFVqFF6ybD aSZg== X-Gm-Message-State: AODbwcC47Gmlks+udqubp3kyMnoswS+LA22X6j45BLf/Kc65wFgtmDY/ TpWBqs2mkJNatPxoazaEXjqT0jN+ag== X-Received: by 10.55.142.70 with SMTP id q67mr31497951qkd.247.1496260098823; Wed, 31 May 2017 12:48:18 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20170524200941.GA30586@lucon.org> References: <20170524200941.GA30586@lucon.org> From: "H.J. Lu" Date: Wed, 31 May 2017 19:48:00 -0000 Message-ID: Subject: Re: [PATCH] x86: Don't use dl_x86_cpu_features in cacheinfo.c To: GNU C Library Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2017-05/txt/msg00914.txt.bz2 On Wed, May 24, 2017 at 1:09 PM, H.J. Lu wrote: > Since cpu_features is available, use it instead of dl_x86_cpu_features. > > Any comments? Any objections? > H.J. > --- > * sysdeps/x86/cacheinfo.c (intel_check_word): Accept cpu_features > and use it instead of dl_x86_cpu_features. > (handle_intel): Replace maxidx with cpu_features. Pass > cpu_features to intel_check_word. > (__cache_sysconf): Pass cpu_features to handle_intel. > (init_cacheinfo): Likewise. Use cpu_features instead of > dl_x86_cpu_features. > --- > sysdeps/x86/cacheinfo.c | 37 ++++++++++++++++++++++--------------- > 1 file changed, 22 insertions(+), 15 deletions(-) > > diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c > index 321fbb6..a46dd4d 100644 > --- a/sysdeps/x86/cacheinfo.c > +++ b/sysdeps/x86/cacheinfo.c > @@ -126,7 +126,8 @@ intel_02_known_compare (const void *p1, const void *p2) > static long int > __attribute__ ((noinline)) > intel_check_word (int name, unsigned int value, bool *has_level_2, > - bool *no_level_2_or_3) > + bool *no_level_2_or_3, > + const struct cpu_features *cpu_features) > { > if ((value & 0x80000000) != 0) > /* The register value is reserved. */ > @@ -204,8 +205,8 @@ intel_check_word (int name, unsigned int value, bool *has_level_2, > /* Intel reused this value. For family 15, model 6 it > specifies the 3rd level cache. Otherwise the 2nd > level cache. */ > - unsigned int family = GLRO(dl_x86_cpu_features).family; > - unsigned int model = GLRO(dl_x86_cpu_features).model; > + unsigned int family = cpu_features->family; > + unsigned int model = cpu_features->model; > > if (family == 15 && model == 6) > { > @@ -255,8 +256,10 @@ intel_check_word (int name, unsigned int value, bool *has_level_2, > > > static long int __attribute__ ((noinline)) > -handle_intel (int name, unsigned int maxidx) > +handle_intel (int name, const struct cpu_features *cpu_features) > { > + unsigned int maxidx = cpu_features->max_cpuid; > + > /* Return -1 for older CPUs. */ > if (maxidx < 2) > return -1; > @@ -287,19 +290,23 @@ handle_intel (int name, unsigned int maxidx) > } > > /* Process the individual registers' value. */ > - result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3); > + result = intel_check_word (name, eax, &has_level_2, > + &no_level_2_or_3, cpu_features); > if (result != 0) > return result; > > - result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3); > + result = intel_check_word (name, ebx, &has_level_2, > + &no_level_2_or_3, cpu_features); > if (result != 0) > return result; > > - result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3); > + result = intel_check_word (name, ecx, &has_level_2, > + &no_level_2_or_3, cpu_features); > if (result != 0) > return result; > > - result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3); > + result = intel_check_word (name, edx, &has_level_2, > + &no_level_2_or_3, cpu_features); > if (result != 0) > return result; > } > @@ -437,7 +444,7 @@ __cache_sysconf (int name) > const struct cpu_features *cpu_features = __get_cpu_features (); > > if (cpu_features->kind == arch_kind_intel) > - return handle_intel (name, cpu_features->max_cpuid); > + return handle_intel (name, cpu_features); > > if (cpu_features->kind == arch_kind_amd) > return handle_amd (name); > @@ -494,14 +501,14 @@ init_cacheinfo (void) > > if (cpu_features->kind == arch_kind_intel) > { > - data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid); > + data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features); > > - long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid); > + long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features); > bool inclusive_cache = true; > > /* Try L3 first. */ > level = 3; > - shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid); > + shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features); > > /* Number of logical processors sharing L2 cache. */ > int threads_l2; > @@ -531,8 +538,8 @@ init_cacheinfo (void) > highest cache level. */ > if (max_cpuid >= 4) > { > - unsigned int family = GLRO(dl_x86_cpu_features).family; > - unsigned int model = GLRO(dl_x86_cpu_features).model; > + unsigned int family = cpu_features->family; > + unsigned int model = cpu_features->model; > > int i = 0; > > @@ -675,7 +682,7 @@ intel_bug_no_cache_info: > level. */ > > threads > - = ((GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].ebx > + = ((cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx > >> 16) & 0xff); > } > > -- > 2.9.4 > -- H.J.