From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by sourceware.org (Postfix) with ESMTPS id 5C3D7385742E for ; Wed, 29 Jun 2022 21:02:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5C3D7385742E Received: by mail-pg1-x52c.google.com with SMTP id g4so9558711pgc.1 for ; Wed, 29 Jun 2022 14:02:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=RBjpHwFQ0AVwvTpI8DFJrahIJyr3vUMVThVvT4YMDjU=; b=laN8vOddPNTRFeFeeK3Ifa6VVtSoac4Qyq6LUPnfTOfB1k9v5sep1gWpqPWYfP4bDu ZbcttLyr8JmNPG7W/10e2hbpyt9c1ADganDpmTI+H4s4PYnv65tm9dUc9Q166wekN1Ti FwbSdGZzwZqyauG6N+ljcWTu9NKWx2PhED3KLwAx0hQBMorzPrOsWcuY34X2cCnmp1TA lUWU2/6T65g8OADBDyPAEkGFtXnbX757aQS3c0KbWT3/+itjtvdUnYhSN8e7i2v9WAKW 65qeIGc3iXrRqfi9AuCOJ4IUNBbugsd/bvm0T9a8ZuJu0PWMywIerPGUAKeuVKqgWkP2 RFwA== X-Gm-Message-State: AJIora8o5xtP4GhRa0OqvsBLP64JRt2AGGaRqKzDSpd1hlOzjZDGCxiH tNRIJ+6pU/5nvg1NoUKMdqQdInwjozvqnVMQR4VES/xM X-Google-Smtp-Source: AGRyM1uSrRCNwkb4+WN3ad06hP/68HvpeAdgpUj8yjSmHyxGwgKy8UONQR1Z5a/CQrLymk3ngoTFGkbg1MGVKtvKiJs= X-Received: by 2002:a05:6a00:14c4:b0:525:9341:288 with SMTP id w4-20020a056a0014c400b0052593410288mr12187405pfu.1.1656536564317; Wed, 29 Jun 2022 14:02:44 -0700 (PDT) MIME-Version: 1.0 References: <20220629202223.293961-1-goldstein.w.n@gmail.com> <20220629204206.567763-1-goldstein.w.n@gmail.com> In-Reply-To: <20220629204206.567763-1-goldstein.w.n@gmail.com> From: "H.J. Lu" Date: Wed, 29 Jun 2022 14:02:08 -0700 Message-ID: Subject: Re: [PATCH v3] x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments To: Noah Goldstein Cc: GNU C Library , "Carlos O'Donell" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3025.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Jun 2022 21:02:47 -0000 On Wed, Jun 29, 2022 at 1:42 PM Noah Goldstein wrote: > > From: "H.J. Lu" > > Properly indent X86_IFUNC_IMPL_ADD_VN arguments for memchr, rawmemchr > and wmemchr. > > Co-authored-by: H.J. Lu > --- > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 99 +++++++++++----------- > 1 file changed, 51 insertions(+), 48 deletions(-) > > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > index 85b17480e5..adf7d4bafd 100644 > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c > @@ -59,26 +59,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > /* Support sysdeps/x86_64/multiarch/memchr.c. */ > IFUNC_IMPL (i, name, memchr, > X86_IFUNC_IMPL_ADD_V4 (array, i, memchr, > - (CPU_FEATURE_USABLE (AVX512VL) > - && CPU_FEATURE_USABLE (AVX512BW) > - && CPU_FEATURE_USABLE (BMI2)), > - __memchr_evex) > + (CPU_FEATURE_USABLE (AVX512VL) > + && CPU_FEATURE_USABLE (AVX512BW) > + && CPU_FEATURE_USABLE (BMI2)), > + __memchr_evex) > X86_IFUNC_IMPL_ADD_V4 (array, i, memchr, > - (CPU_FEATURE_USABLE (AVX512VL) > - && CPU_FEATURE_USABLE (AVX512BW) > - && CPU_FEATURE_USABLE (BMI2)), > - __memchr_evex_rtm) > + (CPU_FEATURE_USABLE (AVX512VL) > + && CPU_FEATURE_USABLE (AVX512BW) > + && CPU_FEATURE_USABLE (BMI2)), > + __memchr_evex_rtm) > X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, > - CPU_FEATURE_USABLE (AVX2), > - __memchr_avx2) > + CPU_FEATURE_USABLE (AVX2), > + __memchr_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, > - (CPU_FEATURE_USABLE (AVX2) > - && CPU_FEATURE_USABLE (RTM)), > - __memchr_avx2_rtm) > - /* Can be lowered to V1 if a V2 implementation is added. */ > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (RTM)), > + __memchr_avx2_rtm) > + /* ISA V2 wrapper for SSE2 implementation because the SSE2 > + implementation is also used at ISA level 2. */ > X86_IFUNC_IMPL_ADD_V2 (array, i, memchr, > - 1, > - __memchr_sse2)) > + 1, > + __memchr_sse2)) > > /* Support sysdeps/x86_64/multiarch/memcmp.c. */ > IFUNC_IMPL (i, name, memcmp, > @@ -321,26 +322,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */ > IFUNC_IMPL (i, name, rawmemchr, > X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr, > - (CPU_FEATURE_USABLE (AVX512VL) > - && CPU_FEATURE_USABLE (AVX512BW) > - && CPU_FEATURE_USABLE (BMI2)), > - __rawmemchr_evex) > + (CPU_FEATURE_USABLE (AVX512VL) > + && CPU_FEATURE_USABLE (AVX512BW) > + && CPU_FEATURE_USABLE (BMI2)), > + __rawmemchr_evex) > X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr, > - (CPU_FEATURE_USABLE (AVX512VL) > - && CPU_FEATURE_USABLE (AVX512BW) > - && CPU_FEATURE_USABLE (BMI2)), > - __rawmemchr_evex_rtm) > + (CPU_FEATURE_USABLE (AVX512VL) > + && CPU_FEATURE_USABLE (AVX512BW) > + && CPU_FEATURE_USABLE (BMI2)), > + __rawmemchr_evex_rtm) > X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, > - CPU_FEATURE_USABLE (AVX2), > - __rawmemchr_avx2) > + CPU_FEATURE_USABLE (AVX2), > + __rawmemchr_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, > - (CPU_FEATURE_USABLE (AVX2) > - && CPU_FEATURE_USABLE (RTM)), > - __rawmemchr_avx2_rtm) > - /* Can be lowered to V1 if a V2 implementation is added. */ > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (RTM)), > + __rawmemchr_avx2_rtm) > + /* ISA V2 wrapper for SSE2 implementation because the SSE2 > + implementation is also used at ISA level 2. */ > X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr, > - 1, > - __rawmemchr_sse2)) > + 1, > + __rawmemchr_sse2)) > > /* Support sysdeps/x86_64/multiarch/strlen.c. */ > IFUNC_IMPL (i, name, strlen, > @@ -790,26 +792,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, > /* Support sysdeps/x86_64/multiarch/wmemchr.c. */ > IFUNC_IMPL (i, name, wmemchr, > X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr, > - (CPU_FEATURE_USABLE (AVX512VL) > - && CPU_FEATURE_USABLE (AVX512BW) > - && CPU_FEATURE_USABLE (BMI2)), > - __wmemchr_evex) > + (CPU_FEATURE_USABLE (AVX512VL) > + && CPU_FEATURE_USABLE (AVX512BW) > + && CPU_FEATURE_USABLE (BMI2)), > + __wmemchr_evex) > X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr, > - (CPU_FEATURE_USABLE (AVX512VL) > - && CPU_FEATURE_USABLE (AVX512BW) > - && CPU_FEATURE_USABLE (BMI2)), > - __wmemchr_evex_rtm) > + (CPU_FEATURE_USABLE (AVX512VL) > + && CPU_FEATURE_USABLE (AVX512BW) > + && CPU_FEATURE_USABLE (BMI2)), > + __wmemchr_evex_rtm) > X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, > - CPU_FEATURE_USABLE (AVX2), > - __wmemchr_avx2) > + CPU_FEATURE_USABLE (AVX2), > + __wmemchr_avx2) > X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, > - (CPU_FEATURE_USABLE (AVX2) > - && CPU_FEATURE_USABLE (RTM)), > - __wmemchr_avx2_rtm) > - /* Can be lowered to V1 if a V2 implementation is added. */ > + (CPU_FEATURE_USABLE (AVX2) > + && CPU_FEATURE_USABLE (RTM)), > + __wmemchr_avx2_rtm) > + /* ISA V2 wrapper for SSE2 implementation because the SSE2 > + implementation is also used at ISA level 2. */ > X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr, > - 1, > - __wmemchr_sse2)) > + 1, > + __wmemchr_sse2)) > > /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */ > IFUNC_IMPL (i, name, wmemcmp, > -- > 2.34.1 > LGTM. Thanks. -- H.J.