* [PATCH v2] x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments
@ 2022-06-29 20:22 Noah Goldstein
2022-06-29 20:26 ` H.J. Lu
2022-06-29 20:42 ` [PATCH v3] " Noah Goldstein
0 siblings, 2 replies; 5+ messages in thread
From: Noah Goldstein @ 2022-06-29 20:22 UTC (permalink / raw)
To: libc-alpha
From: "H.J. Lu" <hjl.tools@gmail.com>
Properly indent X86_IFUNC_IMPL_ADD_VN arguments for memchr, rawmemchr
and wmemchr.
Co-authored-by: H.J. Lu <hjl.tools@gmail.com>
---
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 99 +++++++++++-----------
1 file changed, 51 insertions(+), 48 deletions(-)
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 1452b2809e..119f5f040b 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -58,26 +58,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __memchr_evex)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __memchr_evex)
X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __memchr_evex_rtm)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __memchr_evex_rtm)
X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- /* Can be lowered to V1 if a V2 implementation is added. */
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* ISA V2 wrapper for sse2 implementation because the sse2
+ implementation is also used at ISA level 2. */
X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
- 1,
- __memchr_sse2))
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -315,26 +316,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __rawmemchr_evex)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __rawmemchr_evex)
X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __rawmemchr_evex_rtm)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __rawmemchr_evex_rtm)
X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- /* Can be lowered to V1 if a V2 implementation is added. */
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* ISA V2 wrapper for sse2 implementation because the sse2
+ implementation is also used at ISA level 2. */
X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
- 1,
- __rawmemchr_sse2))
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -784,26 +786,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __wmemchr_evex)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __wmemchr_evex)
X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __wmemchr_evex_rtm)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __wmemchr_evex_rtm)
X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- /* Can be lowered to V1 if a V2 implementation is added. */
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* ISA V2 wrapper for sse2 implementation because the sse2
+ implementation is also used at ISA level 2. */
X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
- 1,
- __wmemchr_sse2))
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments
2022-06-29 20:22 [PATCH v2] x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments Noah Goldstein
@ 2022-06-29 20:26 ` H.J. Lu
2022-06-29 20:42 ` Noah Goldstein
2022-06-29 20:42 ` [PATCH v3] " Noah Goldstein
1 sibling, 1 reply; 5+ messages in thread
From: H.J. Lu @ 2022-06-29 20:26 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 29, 2022 at 1:22 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> From: "H.J. Lu" <hjl.tools@gmail.com>
>
> Properly indent X86_IFUNC_IMPL_ADD_VN arguments for memchr, rawmemchr
> and wmemchr.
>
> Co-authored-by: H.J. Lu <hjl.tools@gmail.com>
> ---
> sysdeps/x86_64/multiarch/ifunc-impl-list.c | 99 +++++++++++-----------
> 1 file changed, 51 insertions(+), 48 deletions(-)
>
> diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> index 1452b2809e..119f5f040b 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> @@ -58,26 +58,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> /* Support sysdeps/x86_64/multiarch/memchr.c. */
> IFUNC_IMPL (i, name, memchr,
> X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __memchr_evex)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __memchr_evex)
> X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __memchr_evex_rtm)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __memchr_evex_rtm)
> X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __memchr_avx2)
> + CPU_FEATURE_USABLE (AVX2),
> + __memchr_avx2)
> X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __memchr_avx2_rtm)
> - /* Can be lowered to V1 if a V2 implementation is added. */
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __memchr_avx2_rtm)
> + /* ISA V2 wrapper for sse2 implementation because the sse2
It should be SSE2, not sse2.
> + implementation is also used at ISA level 2. */
> X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> - 1,
> - __memchr_sse2))
> + 1,
> + __memchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> IFUNC_IMPL (i, name, memcmp,
> @@ -315,26 +316,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> IFUNC_IMPL (i, name, rawmemchr,
> X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __rawmemchr_evex)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __rawmemchr_evex)
> X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __rawmemchr_evex_rtm)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __rawmemchr_evex_rtm)
> X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __rawmemchr_avx2)
> + CPU_FEATURE_USABLE (AVX2),
> + __rawmemchr_avx2)
> X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __rawmemchr_avx2_rtm)
> - /* Can be lowered to V1 if a V2 implementation is added. */
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __rawmemchr_avx2_rtm)
> + /* ISA V2 wrapper for sse2 implementation because the sse2
> + implementation is also used at ISA level 2. */
> X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> - 1,
> - __rawmemchr_sse2))
> + 1,
> + __rawmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/strlen.c. */
> IFUNC_IMPL (i, name, strlen,
> @@ -784,26 +786,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> IFUNC_IMPL (i, name, wmemchr,
> X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __wmemchr_evex)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __wmemchr_evex)
> X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __wmemchr_evex_rtm)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __wmemchr_evex_rtm)
> X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __wmemchr_avx2)
> + CPU_FEATURE_USABLE (AVX2),
> + __wmemchr_avx2)
> X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __wmemchr_avx2_rtm)
> - /* Can be lowered to V1 if a V2 implementation is added. */
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __wmemchr_avx2_rtm)
> + /* ISA V2 wrapper for sse2 implementation because the sse2
> + implementation is also used at ISA level 2. */
> X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> - 1,
> - __wmemchr_sse2))
> + 1,
> + __wmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> IFUNC_IMPL (i, name, wmemcmp,
> --
> 2.34.1
>
--
H.J.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments
2022-06-29 20:26 ` H.J. Lu
@ 2022-06-29 20:42 ` Noah Goldstein
0 siblings, 0 replies; 5+ messages in thread
From: Noah Goldstein @ 2022-06-29 20:42 UTC (permalink / raw)
To: H.J. Lu; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 29, 2022 at 1:27 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Wed, Jun 29, 2022 at 1:22 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > From: "H.J. Lu" <hjl.tools@gmail.com>
> >
> > Properly indent X86_IFUNC_IMPL_ADD_VN arguments for memchr, rawmemchr
> > and wmemchr.
> >
> > Co-authored-by: H.J. Lu <hjl.tools@gmail.com>
> > ---
> > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 99 +++++++++++-----------
> > 1 file changed, 51 insertions(+), 48 deletions(-)
> >
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > index 1452b2809e..119f5f040b 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > @@ -58,26 +58,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > /* Support sysdeps/x86_64/multiarch/memchr.c. */
> > IFUNC_IMPL (i, name, memchr,
> > X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > - (CPU_FEATURE_USABLE (AVX512VL)
> > - && CPU_FEATURE_USABLE (AVX512BW)
> > - && CPU_FEATURE_USABLE (BMI2)),
> > - __memchr_evex)
> > + (CPU_FEATURE_USABLE (AVX512VL)
> > + && CPU_FEATURE_USABLE (AVX512BW)
> > + && CPU_FEATURE_USABLE (BMI2)),
> > + __memchr_evex)
> > X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> > - (CPU_FEATURE_USABLE (AVX512VL)
> > - && CPU_FEATURE_USABLE (AVX512BW)
> > - && CPU_FEATURE_USABLE (BMI2)),
> > - __memchr_evex_rtm)
> > + (CPU_FEATURE_USABLE (AVX512VL)
> > + && CPU_FEATURE_USABLE (AVX512BW)
> > + && CPU_FEATURE_USABLE (BMI2)),
> > + __memchr_evex_rtm)
> > X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __memchr_avx2)
> > + CPU_FEATURE_USABLE (AVX2),
> > + __memchr_avx2)
> > X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __memchr_avx2_rtm)
> > - /* Can be lowered to V1 if a V2 implementation is added. */
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __memchr_avx2_rtm)
> > + /* ISA V2 wrapper for sse2 implementation because the sse2
>
> It should be SSE2, not sse2.
Fixed in V3.
>
> > + implementation is also used at ISA level 2. */
> > X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> > - 1,
> > - __memchr_sse2))
> > + 1,
> > + __memchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> > IFUNC_IMPL (i, name, memcmp,
> > @@ -315,26 +316,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> > IFUNC_IMPL (i, name, rawmemchr,
> > X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > - (CPU_FEATURE_USABLE (AVX512VL)
> > - && CPU_FEATURE_USABLE (AVX512BW)
> > - && CPU_FEATURE_USABLE (BMI2)),
> > - __rawmemchr_evex)
> > + (CPU_FEATURE_USABLE (AVX512VL)
> > + && CPU_FEATURE_USABLE (AVX512BW)
> > + && CPU_FEATURE_USABLE (BMI2)),
> > + __rawmemchr_evex)
> > X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> > - (CPU_FEATURE_USABLE (AVX512VL)
> > - && CPU_FEATURE_USABLE (AVX512BW)
> > - && CPU_FEATURE_USABLE (BMI2)),
> > - __rawmemchr_evex_rtm)
> > + (CPU_FEATURE_USABLE (AVX512VL)
> > + && CPU_FEATURE_USABLE (AVX512BW)
> > + && CPU_FEATURE_USABLE (BMI2)),
> > + __rawmemchr_evex_rtm)
> > X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __rawmemchr_avx2)
> > + CPU_FEATURE_USABLE (AVX2),
> > + __rawmemchr_avx2)
> > X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __rawmemchr_avx2_rtm)
> > - /* Can be lowered to V1 if a V2 implementation is added. */
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __rawmemchr_avx2_rtm)
> > + /* ISA V2 wrapper for sse2 implementation because the sse2
> > + implementation is also used at ISA level 2. */
> > X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> > - 1,
> > - __rawmemchr_sse2))
> > + 1,
> > + __rawmemchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/strlen.c. */
> > IFUNC_IMPL (i, name, strlen,
> > @@ -784,26 +786,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> > IFUNC_IMPL (i, name, wmemchr,
> > X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > - (CPU_FEATURE_USABLE (AVX512VL)
> > - && CPU_FEATURE_USABLE (AVX512BW)
> > - && CPU_FEATURE_USABLE (BMI2)),
> > - __wmemchr_evex)
> > + (CPU_FEATURE_USABLE (AVX512VL)
> > + && CPU_FEATURE_USABLE (AVX512BW)
> > + && CPU_FEATURE_USABLE (BMI2)),
> > + __wmemchr_evex)
> > X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> > - (CPU_FEATURE_USABLE (AVX512VL)
> > - && CPU_FEATURE_USABLE (AVX512BW)
> > - && CPU_FEATURE_USABLE (BMI2)),
> > - __wmemchr_evex_rtm)
> > + (CPU_FEATURE_USABLE (AVX512VL)
> > + && CPU_FEATURE_USABLE (AVX512BW)
> > + && CPU_FEATURE_USABLE (BMI2)),
> > + __wmemchr_evex_rtm)
> > X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > - CPU_FEATURE_USABLE (AVX2),
> > - __wmemchr_avx2)
> > + CPU_FEATURE_USABLE (AVX2),
> > + __wmemchr_avx2)
> > X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> > - (CPU_FEATURE_USABLE (AVX2)
> > - && CPU_FEATURE_USABLE (RTM)),
> > - __wmemchr_avx2_rtm)
> > - /* Can be lowered to V1 if a V2 implementation is added. */
> > + (CPU_FEATURE_USABLE (AVX2)
> > + && CPU_FEATURE_USABLE (RTM)),
> > + __wmemchr_avx2_rtm)
> > + /* ISA V2 wrapper for sse2 implementation because the sse2
> > + implementation is also used at ISA level 2. */
> > X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> > - 1,
> > - __wmemchr_sse2))
> > + 1,
> > + __wmemchr_sse2))
> >
> > /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> > IFUNC_IMPL (i, name, wmemcmp,
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3] x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments
2022-06-29 20:22 [PATCH v2] x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments Noah Goldstein
2022-06-29 20:26 ` H.J. Lu
@ 2022-06-29 20:42 ` Noah Goldstein
2022-06-29 21:02 ` H.J. Lu
1 sibling, 1 reply; 5+ messages in thread
From: Noah Goldstein @ 2022-06-29 20:42 UTC (permalink / raw)
To: libc-alpha
From: "H.J. Lu" <hjl.tools@gmail.com>
Properly indent X86_IFUNC_IMPL_ADD_VN arguments for memchr, rawmemchr
and wmemchr.
Co-authored-by: H.J. Lu <hjl.tools@gmail.com>
---
sysdeps/x86_64/multiarch/ifunc-impl-list.c | 99 +++++++++++-----------
1 file changed, 51 insertions(+), 48 deletions(-)
diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
index 85b17480e5..adf7d4bafd 100644
--- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
@@ -59,26 +59,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/memchr.c. */
IFUNC_IMPL (i, name, memchr,
X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __memchr_evex)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __memchr_evex)
X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __memchr_evex_rtm)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __memchr_evex_rtm)
X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
- CPU_FEATURE_USABLE (AVX2),
- __memchr_avx2)
+ CPU_FEATURE_USABLE (AVX2),
+ __memchr_avx2)
X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __memchr_avx2_rtm)
- /* Can be lowered to V1 if a V2 implementation is added. */
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __memchr_avx2_rtm)
+ /* ISA V2 wrapper for SSE2 implementation because the SSE2
+ implementation is also used at ISA level 2. */
X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
- 1,
- __memchr_sse2))
+ 1,
+ __memchr_sse2))
/* Support sysdeps/x86_64/multiarch/memcmp.c. */
IFUNC_IMPL (i, name, memcmp,
@@ -321,26 +322,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
IFUNC_IMPL (i, name, rawmemchr,
X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __rawmemchr_evex)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __rawmemchr_evex)
X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __rawmemchr_evex_rtm)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __rawmemchr_evex_rtm)
X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __rawmemchr_avx2)
+ CPU_FEATURE_USABLE (AVX2),
+ __rawmemchr_avx2)
X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __rawmemchr_avx2_rtm)
- /* Can be lowered to V1 if a V2 implementation is added. */
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __rawmemchr_avx2_rtm)
+ /* ISA V2 wrapper for SSE2 implementation because the SSE2
+ implementation is also used at ISA level 2. */
X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
- 1,
- __rawmemchr_sse2))
+ 1,
+ __rawmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/strlen.c. */
IFUNC_IMPL (i, name, strlen,
@@ -790,26 +792,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
/* Support sysdeps/x86_64/multiarch/wmemchr.c. */
IFUNC_IMPL (i, name, wmemchr,
X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __wmemchr_evex)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __wmemchr_evex)
X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX512VL)
- && CPU_FEATURE_USABLE (AVX512BW)
- && CPU_FEATURE_USABLE (BMI2)),
- __wmemchr_evex_rtm)
+ (CPU_FEATURE_USABLE (AVX512VL)
+ && CPU_FEATURE_USABLE (AVX512BW)
+ && CPU_FEATURE_USABLE (BMI2)),
+ __wmemchr_evex_rtm)
X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
- CPU_FEATURE_USABLE (AVX2),
- __wmemchr_avx2)
+ CPU_FEATURE_USABLE (AVX2),
+ __wmemchr_avx2)
X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
- (CPU_FEATURE_USABLE (AVX2)
- && CPU_FEATURE_USABLE (RTM)),
- __wmemchr_avx2_rtm)
- /* Can be lowered to V1 if a V2 implementation is added. */
+ (CPU_FEATURE_USABLE (AVX2)
+ && CPU_FEATURE_USABLE (RTM)),
+ __wmemchr_avx2_rtm)
+ /* ISA V2 wrapper for SSE2 implementation because the SSE2
+ implementation is also used at ISA level 2. */
X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
- 1,
- __wmemchr_sse2))
+ 1,
+ __wmemchr_sse2))
/* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
IFUNC_IMPL (i, name, wmemcmp,
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments
2022-06-29 20:42 ` [PATCH v3] " Noah Goldstein
@ 2022-06-29 21:02 ` H.J. Lu
0 siblings, 0 replies; 5+ messages in thread
From: H.J. Lu @ 2022-06-29 21:02 UTC (permalink / raw)
To: Noah Goldstein; +Cc: GNU C Library, Carlos O'Donell
On Wed, Jun 29, 2022 at 1:42 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> From: "H.J. Lu" <hjl.tools@gmail.com>
>
> Properly indent X86_IFUNC_IMPL_ADD_VN arguments for memchr, rawmemchr
> and wmemchr.
>
> Co-authored-by: H.J. Lu <hjl.tools@gmail.com>
> ---
> sysdeps/x86_64/multiarch/ifunc-impl-list.c | 99 +++++++++++-----------
> 1 file changed, 51 insertions(+), 48 deletions(-)
>
> diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> index 85b17480e5..adf7d4bafd 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> @@ -59,26 +59,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> /* Support sysdeps/x86_64/multiarch/memchr.c. */
> IFUNC_IMPL (i, name, memchr,
> X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __memchr_evex)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __memchr_evex)
> X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __memchr_evex_rtm)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __memchr_evex_rtm)
> X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __memchr_avx2)
> + CPU_FEATURE_USABLE (AVX2),
> + __memchr_avx2)
> X86_IFUNC_IMPL_ADD_V3 (array, i, memchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __memchr_avx2_rtm)
> - /* Can be lowered to V1 if a V2 implementation is added. */
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __memchr_avx2_rtm)
> + /* ISA V2 wrapper for SSE2 implementation because the SSE2
> + implementation is also used at ISA level 2. */
> X86_IFUNC_IMPL_ADD_V2 (array, i, memchr,
> - 1,
> - __memchr_sse2))
> + 1,
> + __memchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/memcmp.c. */
> IFUNC_IMPL (i, name, memcmp,
> @@ -321,26 +322,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */
> IFUNC_IMPL (i, name, rawmemchr,
> X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __rawmemchr_evex)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __rawmemchr_evex)
> X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __rawmemchr_evex_rtm)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __rawmemchr_evex_rtm)
> X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __rawmemchr_avx2)
> + CPU_FEATURE_USABLE (AVX2),
> + __rawmemchr_avx2)
> X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __rawmemchr_avx2_rtm)
> - /* Can be lowered to V1 if a V2 implementation is added. */
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __rawmemchr_avx2_rtm)
> + /* ISA V2 wrapper for SSE2 implementation because the SSE2
> + implementation is also used at ISA level 2. */
> X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr,
> - 1,
> - __rawmemchr_sse2))
> + 1,
> + __rawmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/strlen.c. */
> IFUNC_IMPL (i, name, strlen,
> @@ -790,26 +792,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> /* Support sysdeps/x86_64/multiarch/wmemchr.c. */
> IFUNC_IMPL (i, name, wmemchr,
> X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __wmemchr_evex)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __wmemchr_evex)
> X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
> - (CPU_FEATURE_USABLE (AVX512VL)
> - && CPU_FEATURE_USABLE (AVX512BW)
> - && CPU_FEATURE_USABLE (BMI2)),
> - __wmemchr_evex_rtm)
> + (CPU_FEATURE_USABLE (AVX512VL)
> + && CPU_FEATURE_USABLE (AVX512BW)
> + && CPU_FEATURE_USABLE (BMI2)),
> + __wmemchr_evex_rtm)
> X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> - CPU_FEATURE_USABLE (AVX2),
> - __wmemchr_avx2)
> + CPU_FEATURE_USABLE (AVX2),
> + __wmemchr_avx2)
> X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr,
> - (CPU_FEATURE_USABLE (AVX2)
> - && CPU_FEATURE_USABLE (RTM)),
> - __wmemchr_avx2_rtm)
> - /* Can be lowered to V1 if a V2 implementation is added. */
> + (CPU_FEATURE_USABLE (AVX2)
> + && CPU_FEATURE_USABLE (RTM)),
> + __wmemchr_avx2_rtm)
> + /* ISA V2 wrapper for SSE2 implementation because the SSE2
> + implementation is also used at ISA level 2. */
> X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr,
> - 1,
> - __wmemchr_sse2))
> + 1,
> + __wmemchr_sse2))
>
> /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */
> IFUNC_IMPL (i, name, wmemcmp,
> --
> 2.34.1
>
LGTM.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-06-29 21:02 UTC | newest]
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2022-06-29 20:22 [PATCH v2] x86-64: Properly indent X86_IFUNC_IMPL_ADD_VN arguments Noah Goldstein
2022-06-29 20:26 ` H.J. Lu
2022-06-29 20:42 ` Noah Goldstein
2022-06-29 20:42 ` [PATCH v3] " Noah Goldstein
2022-06-29 21:02 ` H.J. Lu
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