From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 114834 invoked by alias); 25 Oct 2016 14:45:17 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Received: (qmail 114802 invoked by uid 89); 25 Oct 2016 14:45:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=no version=3.3.2 spammy=H*x:iPhone, H*UA:iPhone, Riegel, seconded X-HELO: mail-qk0-f177.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=4VbqbRF8UX3sG3TquqfQq+ug4Aanv+qwrEZFxP4k+Cw=; b=kckOHP5cyRIEBXOFzp8jZ/lv+5Pp72ZXYy1CM6TThy/BjORqpkwDqQdK3AhC50DbwT OvqH9jljrWCbyIptXhWtDXPlEOnBIyw+m9dqhpgXruothEQ3Ajt9m42NaC0S0A19fqpH fWPNK/uVMQhbWahc+9iA+ld8qco4nysVWFKtvN5M/elMVDInYPeUOi8xBKGCCdsQr26H Xec258OBQIa/8PyeSDWAB5Q4vXaPBmLlWXIAAU4Lbde2DYwu7e6j24fb//wM0Az8dVO4 +hlA+F5qSerRm+tA7fvhhKaqV//cepGGednpV6khpO6GT01XEcK5UgLnFZCAZZpnWPcy 4DRg== X-Gm-Message-State: ABUngvf6DTWf/iD/45naHn7fV84bHAAX4tDSWrwy/mw481GmudLeVzAaelpxT5pmi5+wJ8RN X-Received: by 10.55.75.215 with SMTP id y206mr19616971qka.26.1477406694943; Tue, 25 Oct 2016 07:44:54 -0700 (PDT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (1.0) Subject: Re: Remove sparcv8 support From: Adhemerval Zanella In-Reply-To: <580F6D5E.6050600@gaisler.com> Date: Tue, 25 Oct 2016 14:45:00 -0000 Cc: Torvald Riegel , GNU C Library , David Miller , "software@gaisler.com" Content-Transfer-Encoding: quoted-printable Message-Id: References: <48cdf008-b66a-d411-a07a-5a38595978b9@linaro.org> <5809D90E.1090005@gaisler.com> <1477329945.7146.95.camel@localhost.localdomain> <8224de36-8a30-980c-697b-8e4cae481184@linaro.org> <580F6D5E.6050600@gaisler.com> To: Andreas Larsson X-SW-Source: 2016-10/txt/msg00427.txt.bz2 > On 25 Oct 2016, at 12:34, Andreas Larsson wrote: >=20 >> On 2016-10-24 19:42, Adhemerval Zanella wrote: >>=20 >>=20 >>> On 24/10/2016 15:25, Torvald Riegel wrote: >>>> On Fri, 2016-10-21 at 10:59 +0200, Andreas Larsson wrote: >>>>> On 2016-10-20 21:47, Adhemerval Zanella wrote: >>>>> The sparcv8 build is broken since GLIBC 2.23 due the new pthread >>>>> barrier implementation [1] and since then there is no thread or >>>>> interest on fixing it (Torvald has suggested some options on >>>>> 2.23 release thread). It won't help with both new pthread rdlock >>>>> and cond implementation, although I would expect that it relies >>>>> on same atomic primitive that was not present for pthread barrier. >>>>>=20 >>>>> AFAIK, recent commercial sparc chips from Oracle all supports >>>>> sparcv9. The only somewhat recent sparc chip with just sparcv8 >>>>> support is LEON4, which I really doubt it cares for glibc support. >>>>=20 >>>> Hi! >>>>=20 >>>> We do care about GLIBC support for many different LEON3 and LEON4 >>>> systems. GLIBC support for sparcv8 is important for us and it is >>>> important for our customers. Both LEON3 and LEON4 are continuously used >>>> in new hardware designs. >>>=20 >>> If you do care about it, it would be nice if you could (help) maintain >>> sparcv8 (e.g., regularly testing most recent glibc on sparcv8, at the >>> very least early during the freeze of each release). This ensures that >>> you won't get surprises such as this one, when nobody else is spending >>> resources on it. >>>=20 >>>> We are not always using the latest version of GLIBC (the latest step we >>>> took was to GLIBC 2.20), so unfortunately we missed this issue. We will >>>> look into what the extent of the missing support is. Any pointers are >>>> most welcome. >>>>=20 >>>> Do you have a link to the suggested options on the 2.23 release thread? >>>> I dug around a bit in the archives, but did not find it. >>>>=20 >>>> (As a side note, most of the recent LEON3 and LEON4 chips have CAS >>>> instruction support, but pure sparcv8 support is of course the baselin= e.) >>>=20 >>> Yes, the lack of CAS is the major problem I am aware of. If the chips >>> you mention do support CAS, then a patch that adds support for the >>> CAS-based atomic operations in glibc would fix the barrier problem >>> (because the generic barrier should just work). The patch would also >>> have to add configure bits or whatever would be appropriate so that >>> glibc can figure out whether it is supposed to be run on a sparcv8 with >>> or without CAS. >>>=20 >>> What about stopping support for plain sparcv8, and keeping to support >>> sparcv8+CAS provided that we have a (group of) maintainer(s) for the >>> latter that can tend to the minimal responsibilities of an arch >>> maintainer and has the time to do that? >>=20 >> At least the build for sparcv9-linux-gnu with -mcpu=3Dleon3 finishes, >> although I am not sure if it correctly runs on leon processors. >> And I seconded Tovarld's suggestion about stop maintaining plain >> sparcv8 and set sparcv8+CAS as the base supported sparc32. >=20 > I have mixed feelings about this, but it is certainly better than > throwing out sparcv8 outright. >> As pointed out by David Miller, correct support for plain sparcv8 >> could really only be provided with kernel supported. And when >> it lands on kernel side, it should work effortlessly with a >> sparcv8 + cas glibc build. >=20 > What do you mean by "work effortlessly with a sparcv8 + cas glibc > build"? Meaning that even if underlying hardware does not support correct CAS, kern= el emulation will provide it and thus a default GLIBC sparc32 build will wo= rk regardless.