RE: [PATCH v2 2/2] Aarch64: Add new memset for Qualcomm's 0ryon-1 core

["Andrew Pinski (QUIC)" <quic_apinski@quicinc.com>]

> -----Original Message-----
> From: Florian Weimer <fweimer@redhat.com>
> Sent: Tuesday, May 14, 2024 12:37 AM
> To: Andrew Pinski (QUIC) <quic_apinski@quicinc.com>
> Cc: libc-alpha@sourceware.org
> Subject: Re: [PATCH v2 2/2] Aarch64: Add new memset for Qualcomm's
> 0ryon-1 core
> 
> * Andrew Pinski:
> 
> >> -----Original Message-----
> >> From: Florian Weimer <fweimer@redhat.com>
> >> Sent: Monday, May 13, 2024 6:49 AM
> >> To: Andrew Pinski (QUIC) <quic_apinski@quicinc.com>
> >> Cc: libc-alpha@sourceware.org
> >> Subject: Re: [PATCH v2 2/2] Aarch64: Add new memset for Qualcomm's
> >> 0ryon-1 core
> >>
> >> * Andrew Pinski:
> >>
> >> > Qualcom's new core, oryon-1, has a different characteristics for
> >> > memset than the current versions of memset. For non-zero, larger
> >> > sizes, using GPRs rather than the SIMD stores is ~30% faster.
> >> > For even larger sizes, using the nontemporal stores is needed not
> >> > to polute the L1/L2 caches.
> >>
> >> NB: Commit subject has 0ryon with a zero instead of an O.  Not sure
> >> if this is intentional.
> >
> > No, it was a typo, the `o` is right below the 0 on the keyboard and I
> > did not notice that typo until you mentioned it.  Should I submit a
> > new patch with the typo fixed in the subject line or will the person
> > committing it will fix it?
> 
> If found some other nits, so maybe repost it?  We can then consider applying
> it.

Ok, I will fix it and resubmit.

> 
> I suppose you will be around to maintain these implementations?

Yes I will be around to maintain these implementations though is this a new requirement since it was not asked of the other implementations that were added in previous years. 

Thanks,
Andrew Pinski

> 
> Thanks,
> Florian