From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-vi1eur04on2082.outbound.protection.outlook.com [40.107.8.82]) by sourceware.org (Postfix) with ESMTPS id 72BE93858D32 for ; Fri, 10 Nov 2023 17:53:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 72BE93858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 72BE93858D32 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.8.82 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1699638831; cv=pass; b=JTW4mHOulVYHwS8Ad39ezjg8Dgcrbei1bk6C9o0W0e/rgXhqMmGQgEtPJ3p3UKBTQN5nF5CiruA096YVvUWnq0NEDi3D0gJzz4cpfhFB8RD/A/XaBJszcYZsKmX4z21jDgR2tA7OIGlZJlfWTQjNKn3ND+hMSV9KEXMdWyxfMYI= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1699638831; c=relaxed/simple; bh=+UEP08UTFPpB8ffRWGR34WqFp0RDltiE1T29QXV0Ewk=; h=DKIM-Signature:DKIM-Signature:Date:From:To:Subject:Message-ID: MIME-Version; b=dsGHNHiIB25iN3tGSJSnpp3Zk7b6njRRWfjYrmSHJszKNYgyN/cSCb4VTZVdgZfgKv107/qW6BHwDeVeuVcdfsStWWqfZSk344laywoDa3hEz3YTnYIlR5gdOxd4wrODMD2XVtGVsBdQT0WjUeAIfSrjzjpoV6NgOV8LiSxS6zE= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=YcArZCdjRyA9IhRhC2I7qeQjcKs1/4jV11pbNGo6hywHYN6inekz1yTQCMgnSsFNAMT+j0OuLNT4Tt9SpD/FcYlYw+ruDOUwBKN4ZYZFWTOc+3Pyx4x5r5/NV71e5P7DNvMO9IxTc/jwP+30tx33+HSTR+/Hay9ReC7c/nybNNXhEE7mwcTUfH7sH3oREOyEPZUpaxnPyVrWYHrpASr0XVxEv6DsfPGogO86Ys1O5A6U1ZLMPQyBZz1t6Mast3Yyn5IL1QExmAKS2a8FI07Hnb+K9FESz1GoleC02sEdOutdKAf/cx2et3cUytwIxLUh1eKoUk31NNYRqqU54Vq94Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=EDETi7QHcXEO/KF1SYrXsfqQjsH7gPjenMUkAufjRbw=; b=mz53NkGWmZsnw5G1Wdin2ygzpKfp1PAEmSHtHXuFAXkhIuVd7jXObmTlvlOb8e47tjVBo+F3+C0yOmoQK75aHuvEf+1hj6X8x/YIg9Ba/8PDB7eJi1W6V2vLs4gq34m5SshAoK/IFgw6hAsBFEhQm5JI9f4CVxfjQJwefGaiBV01vPGUDhQICfjc5sga5hsV4wdna7IvWS13eh2kGpNlcDBB5U62rhwe4J2+9QHpoxCqpo1eTe4EdKFWsYmlHH4f4ziJRJHdjpLOguAOTXJalOoUPwC5MZ4c1lg6LEHq/aVBgH7E398gZPJcWfPaHeBO/2R9n/GH9is+bxHIvrd66g== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EDETi7QHcXEO/KF1SYrXsfqQjsH7gPjenMUkAufjRbw=; b=fLdpMbofPqXzvG8RTj4Y0DFirnmVLE0Vgd02a71Q8/oVDMPRrpX7XsvGWF4dYUCMH1NOUuPe/X/WICCfa9cS656on4kMZdSQW9EDkBTf4PQSPDaSzTz/7s7N9CKww22S/9RP5gV7JXKOfP+WPdrYZKcy52Yhfbliu6mt624w0V4= Received: from AS9PR07CA0048.eurprd07.prod.outlook.com (2603:10a6:20b:46b::15) by PA6PR08MB10621.eurprd08.prod.outlook.com (2603:10a6:102:3c8::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.18; Fri, 10 Nov 2023 17:53:42 +0000 Received: from AMS0EPF00000191.eurprd05.prod.outlook.com (2603:10a6:20b:46b:cafe::2) by AS9PR07CA0048.outlook.office365.com (2603:10a6:20b:46b::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.19 via Frontend Transport; Fri, 10 Nov 2023 17:53:41 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AMS0EPF00000191.mail.protection.outlook.com (10.167.16.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.16 via Frontend Transport; Fri, 10 Nov 2023 17:53:41 +0000 Received: ("Tessian outbound 26ee1d40577c:v228"); Fri, 10 Nov 2023 17:53:41 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 71badfb508b7cdc7 X-CR-MTA-TID: 64aa7808 Received: from deccb2c21067.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id C25D6D7B-47AE-4F04-84A4-206C12F73EA0.1; Fri, 10 Nov 2023 17:53:33 +0000 Received: from EUR05-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id deccb2c21067.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 10 Nov 2023 17:53:33 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QtBSxutWy/nOR3Ji9ndIqceLC5kczqO1cLlFelNDfJl3p7gYSPsr9/kSSqu1n755n3EYSoF2VglJ9xGtjIKCP06BikHs8r/EOfOy+kHVmVVXLpV3i9FAhN2trsQjhr3v0xkk8g5PV3fj2z84YmJkRi+EFm9DlRivKV+tamO3cFYBqIMPK+U9SP78Mn8mXSvT972ThFDRuh1ZtUJcHMgXq3mSqIVLSfZxIHX8Ou1Q+VzjMd4J88gnr7HwIgv9VEBsqXBFltjsisSSKakEdfr0hpLJeS5bmM6zQ0wNdSOHVcWP4YcJaZsgB97i1C0DuxHV1UBRWZD2i6OXxB/e/9iMDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=EDETi7QHcXEO/KF1SYrXsfqQjsH7gPjenMUkAufjRbw=; b=AAj3yCtIZKwWRBOBP0cgP4wmbnGSjyXqpZumD5ld8O+K8v09hFJMien30dUmt3Rde+DjZzwsgJFaoC7jfxQHZhAcBVzS1TREFBXI0oJKNWMVZpv2j3Mjj9VyIWdBKe/S5Kt0eDH+BBEMPyrFzRVYM7U8zLQy7B5rAasVS6YeT6uy/vS+4h4kVR0mI9B9wtvuVXYkfMqTYFKnyZ8Um2r5U0as9oK3EvMcKzdEB1xISI3qSutllpkCpykbkHIDkcT7wkWg3AjObVcJ7dmJfLdtdfXJJIBLWadL8JzRzcfbPB0iHrI3g4e9BBU29b/mC4qvYt4eWwh8z8PNR0YZgvZ3hQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EDETi7QHcXEO/KF1SYrXsfqQjsH7gPjenMUkAufjRbw=; b=fLdpMbofPqXzvG8RTj4Y0DFirnmVLE0Vgd02a71Q8/oVDMPRrpX7XsvGWF4dYUCMH1NOUuPe/X/WICCfa9cS656on4kMZdSQW9EDkBTf4PQSPDaSzTz/7s7N9CKww22S/9RP5gV7JXKOfP+WPdrYZKcy52Yhfbliu6mt624w0V4= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from DB9PR08MB7179.eurprd08.prod.outlook.com (2603:10a6:10:2cc::19) by AS8PR08MB6696.eurprd08.prod.outlook.com (2603:10a6:20b:395::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.19; Fri, 10 Nov 2023 17:53:31 +0000 Received: from DB9PR08MB7179.eurprd08.prod.outlook.com ([fe80::a991:ac53:e218:e554]) by DB9PR08MB7179.eurprd08.prod.outlook.com ([fe80::a991:ac53:e218:e554%3]) with mapi id 15.20.6954.029; Fri, 10 Nov 2023 17:53:31 +0000 Date: Fri, 10 Nov 2023 17:53:15 +0000 From: Szabolcs Nagy To: Joe Ramsay , Subject: Re: [PATCH 2/6] aarch64: Add vector implementations of acos routines Message-ID: References: <20231103121224.16835-1-Joe.Ramsay@arm.com> <20231103121224.16835-2-Joe.Ramsay@arm.com> Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20231103121224.16835-2-Joe.Ramsay@arm.com> X-ClientProxiedBy: LO3P123CA0010.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:ba::15) To DB9PR08MB7179.eurprd08.prod.outlook.com (2603:10a6:10:2cc::19) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DB9PR08MB7179:EE_|AS8PR08MB6696:EE_|AMS0EPF00000191:EE_|PA6PR08MB10621:EE_ X-MS-Office365-Filtering-Correlation-Id: 91115392-20fa-4186-c00b-08dbe215f9c6 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: dpbqE6DvdJYdIWdP4U3HvfZFkR77Mxto/AYXcv+qGGKxzbDEWSWynQGjXoLQvrm52LevO25lDiywGTgfrMqHEVG8psC/CFEf+h/tPlwqPrAFceAVRQzXT/qEDDAJxT85lTKlzZBVNa0YXGgmmUDeOsmwImmgzmCEq+CRj5442RVq1HxM1I+mGZbapztNLHztvn2bUlQzi/TfJ9LkGN/5gSRezmjo9iJPREvoyQ5ePnsHBMHJ68Kzcr+8Zp5uYTjsFi/2VTD/AMaRHy1P28hyz8l+rsldU3gw4pwUvzImqp8K2BknAIz2QZ81PRw3OLL4k8PVDBN8cO8OfSkIkas01mrB2xTgGuFXoVwdf6f0x9x772+lNJjA7cZAxmOOCrK6fj/WFCPzduVDrrWAHVTQfNV/9I5faL+FbB74SVyGuYQNhUMofnKlNPvXSD+ZRLt0xzGdFO3/CKQy+nzyP7ZHO6+Ih0wh6+EFN6qleEFtTGqJk0SREPadpQ5W99BMXr5gBilTJlLy+XKKV0XI1heYOedWrq0cKS/yM3wY6fj1/LTe5THjV6kpzN9NqM5jTZErAQsP8io2IJxFHWNL0vKtMHqFXJiqaiBXsnmKelX5ECM= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DB9PR08MB7179.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(136003)(376002)(39860400002)(366004)(396003)(346002)(230922051799003)(451199024)(186009)(64100799003)(1800799009)(2616005)(26005)(6486002)(478600001)(8936002)(36756003)(44832011)(8676002)(5660300002)(41300700001)(86362001)(30864003)(2906002)(66946007)(66556008)(66476007)(316002)(110136005)(6506007)(6666004)(6512007)(38100700002)(83380400001)(2004002);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6696 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AMS0EPF00000191.eurprd05.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: d89b28a0-446b-4b8b-281c-08dbe215f36d X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1wfy0ubND+KkRmdAQRXupuiGHPF1y5Hl7BnbYR5gOgcplWe1TazUmGpouY7A/mEqFfrRL/JPF7hQ0UkqPz3IrxEiIQXWg6CoAPKhmuzzCeWdDLBz9uZ3f7vUc8i768lSOPVXWcbMxUWUXGNEedqnpWpCYihkveulbQtAwx3CFnhJKYlGjFGPI189dcZEHaYrhG1BHgemV/OuyyiXiMWWNM1k+xYwOBRhvv6DuDlJkG5oM36rn9DB/gxfQe6cNQ05stk8C5zA/q9b5JHib6j83v8v49e/fWRcx/xCRSvrR8WN4cNzUg8iSO0HHHYZumiPWgR9xqwZThUI5R12vB7E1aUwPrzKNaWp06WdCaaMdJShc7363hx6lbkpveNf2h9bhP3NSkfw/qAQqDMhdOmBB8W1w+lp8lDiA7mxcj1JUSNkUxYd+gaUmIjSJwyxLwJjgMa4XdnBEuqXt8EcYIDjqIBeS43/PLArCCU75CecU5WAQdUQ1SYO0NKX55x/SE/wkC0nSDUxgRgTxP6imx7sBa2Gd3uhdYjRevAIfSYsKJWZW4lfQWVL+pFdVOTUw7K/fkNj2T40mteYeqLgJ3v61VAHF77Yl8hndue9UJkfe4DWds7erScSdYP/aFsJgf06Zgd+WKgEcN5EU567tmqvxyshWVlZRuVFiLV+xtzRlhdSt2E0o6lsc1Uhtwz7rn1HZhGYByoDcX4KWvXWRKMCQ6U/dkG35QlUEHI894s0j1BhYuQuRBuLJxckUlyLR66e X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(396003)(346002)(136003)(39860400002)(230922051799003)(451199024)(1800799009)(82310400011)(186009)(64100799003)(46966006)(36840700001)(40470700004)(40460700003)(47076005)(40480700001)(44832011)(82740400003)(6506007)(8936002)(356005)(8676002)(6486002)(36756003)(81166007)(6666004)(478600001)(41300700001)(36860700001)(6512007)(2906002)(26005)(316002)(83380400001)(110136005)(70586007)(30864003)(70206006)(336012)(2616005)(5660300002)(86362001)(2004002);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2023 17:53:41.5174 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 91115392-20fa-4186-c00b-08dbe215f9c6 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF00000191.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA6PR08MB10621 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The 11/03/2023 12:12, Joe Ramsay wrote: > --- this is OK to commit. Reviewed-by: Szabolcs Nagy > Thanks, > Joe > sysdeps/aarch64/fpu/Makefile | 3 +- > sysdeps/aarch64/fpu/Versions | 4 + > sysdeps/aarch64/fpu/acos_advsimd.c | 122 ++++++++++++++++++ > sysdeps/aarch64/fpu/acos_sve.c | 93 +++++++++++++ > sysdeps/aarch64/fpu/acosf_advsimd.c | 113 ++++++++++++++++ > sysdeps/aarch64/fpu/acosf_sve.c | 86 ++++++++++++ > sysdeps/aarch64/fpu/bits/math-vector.h | 4 + > .../fpu/test-double-advsimd-wrappers.c | 1 + > .../aarch64/fpu/test-double-sve-wrappers.c | 1 + > .../aarch64/fpu/test-float-advsimd-wrappers.c | 1 + > sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 + > sysdeps/aarch64/libm-test-ulps | 8 ++ > .../unix/sysv/linux/aarch64/libmvec.abilist | 4 + > 13 files changed, 440 insertions(+), 1 deletion(-) > create mode 100644 sysdeps/aarch64/fpu/acos_advsimd.c > create mode 100644 sysdeps/aarch64/fpu/acos_sve.c > create mode 100644 sysdeps/aarch64/fpu/acosf_advsimd.c > create mode 100644 sysdeps/aarch64/fpu/acosf_sve.c > > diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile > index d7c0bd2ed5..606fdd804f 100644 > --- a/sysdeps/aarch64/fpu/Makefile > +++ b/sysdeps/aarch64/fpu/Makefile > @@ -1,4 +1,5 @@ > -libmvec-supported-funcs = asin \ > +libmvec-supported-funcs = acos \ > + asin \ > cos \ > exp \ > exp10 \ > diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions > index 0f365a1e2e..1037cd92bd 100644 > --- a/sysdeps/aarch64/fpu/Versions > +++ b/sysdeps/aarch64/fpu/Versions > @@ -18,6 +18,10 @@ libmvec { > _ZGVsMxv_sinf; > } > GLIBC_2.39 { > + _ZGVnN4v_acosf; > + _ZGVnN2v_acos; > + _ZGVsMxv_acosf; > + _ZGVsMxv_acos; > _ZGVnN4v_asinf; > _ZGVnN2v_asin; > _ZGVsMxv_asinf; > diff --git a/sysdeps/aarch64/fpu/acos_advsimd.c b/sysdeps/aarch64/fpu/acos_advsimd.c > new file mode 100644 > index 0000000000..3121cf66b1 > --- /dev/null > +++ b/sysdeps/aarch64/fpu/acos_advsimd.c > @@ -0,0 +1,122 @@ > +/* Double-precision AdvSIMD inverse cos > + > + Copyright (C) 2023 Free Software Foundation, Inc. > + This file is part of the GNU C Library. > + > + The GNU C Library is free software; you can redistribute it and/or > + modify it under the terms of the GNU Lesser General Public > + License as published by the Free Software Foundation; either > + version 2.1 of the License, or (at your option) any later version. > + > + The GNU C Library is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + Lesser General Public License for more details. > + > + You should have received a copy of the GNU Lesser General Public > + License along with the GNU C Library; if not, see > + . */ > + > +#include "v_math.h" > +#include "poly_advsimd_f64.h" > + > +static const struct data > +{ > + float64x2_t poly[12]; > + float64x2_t pi, pi_over_2; > + uint64x2_t abs_mask; > +} data = { > + /* Polynomial approximation of (asin(sqrt(x)) - sqrt(x)) / (x * sqrt(x)) > + on [ 0x1p-106, 0x1p-2 ], relative error: 0x1.c3d8e169p-57. */ > + .poly = { V2 (0x1.555555555554ep-3), V2 (0x1.3333333337233p-4), > + V2 (0x1.6db6db67f6d9fp-5), V2 (0x1.f1c71fbd29fbbp-6), > + V2 (0x1.6e8b264d467d6p-6), V2 (0x1.1c5997c357e9dp-6), > + V2 (0x1.c86a22cd9389dp-7), V2 (0x1.856073c22ebbep-7), > + V2 (0x1.fd1151acb6bedp-8), V2 (0x1.087182f799c1dp-6), > + V2 (-0x1.6602748120927p-7), V2 (0x1.cfa0dd1f9478p-6), }, > + .pi = V2 (0x1.921fb54442d18p+1), > + .pi_over_2 = V2 (0x1.921fb54442d18p+0), > + .abs_mask = V2 (0x7fffffffffffffff), > +}; > + > +#define AllMask v_u64 (0xffffffffffffffff) > +#define Oneu (0x3ff0000000000000) > +#define Small (0x3e50000000000000) /* 2^-53. */ > + > +#if WANT_SIMD_EXCEPT > +static float64x2_t VPCS_ATTR NOINLINE > +special_case (float64x2_t x, float64x2_t y, uint64x2_t special) > +{ > + return v_call_f64 (acos, x, y, special); > +} > +#endif > + > +/* Double-precision implementation of vector acos(x). > + > + For |x| < Small, approximate acos(x) by pi/2 - x. Small = 2^-53 for correct > + rounding. > + If WANT_SIMD_EXCEPT = 0, Small = 0 and we proceed with the following > + approximation. > + > + For |x| in [Small, 0.5], use an order 11 polynomial P such that the final > + approximation of asin is an odd polynomial: > + > + acos(x) ~ pi/2 - (x + x^3 P(x^2)). > + > + The largest observed error in this region is 1.18 ulps, > + _ZGVnN2v_acos (0x1.fbab0a7c460f6p-2) got 0x1.0d54d1985c068p+0 > + want 0x1.0d54d1985c069p+0. > + > + For |x| in [0.5, 1.0], use same approximation with a change of variable > + > + acos(x) = y + y * z * P(z), with z = (1-x)/2 and y = sqrt(z). > + > + The largest observed error in this region is 1.52 ulps, > + _ZGVnN2v_acos (0x1.23d362722f591p-1) got 0x1.edbbedf8a7d6ep-1 > + want 0x1.edbbedf8a7d6cp-1. */ > +float64x2_t VPCS_ATTR V_NAME_D1 (acos) (float64x2_t x) > +{ > + const struct data *d = ptr_barrier (&data); > + > + float64x2_t ax = vabsq_f64 (x); > + > +#if WANT_SIMD_EXCEPT > + /* A single comparison for One, Small and QNaN. */ > + uint64x2_t special > + = vcgtq_u64 (vsubq_u64 (vreinterpretq_u64_f64 (ax), v_u64 (Small)), > + v_u64 (Oneu - Small)); > + if (__glibc_unlikely (v_any_u64 (special))) > + return special_case (x, x, AllMask); > +#endif > + > + uint64x2_t a_le_half = vcleq_f64 (ax, v_f64 (0.5)); > + > + /* Evaluate polynomial Q(x) = z + z * z2 * P(z2) with > + z2 = x ^ 2 and z = |x| , if |x| < 0.5 > + z2 = (1 - |x|) / 2 and z = sqrt(z2), if |x| >= 0.5. */ > + float64x2_t z2 = vbslq_f64 (a_le_half, vmulq_f64 (x, x), > + vfmaq_f64 (v_f64 (0.5), v_f64 (-0.5), ax)); > + float64x2_t z = vbslq_f64 (a_le_half, ax, vsqrtq_f64 (z2)); > + > + /* Use a single polynomial approximation P for both intervals. */ > + float64x2_t z4 = vmulq_f64 (z2, z2); > + float64x2_t z8 = vmulq_f64 (z4, z4); > + float64x2_t z16 = vmulq_f64 (z8, z8); > + float64x2_t p = v_estrin_11_f64 (z2, z4, z8, z16, d->poly); > + > + /* Finalize polynomial: z + z * z2 * P(z2). */ > + p = vfmaq_f64 (z, vmulq_f64 (z, z2), p); > + > + /* acos(|x|) = pi/2 - sign(x) * Q(|x|), for |x| < 0.5 > + = 2 Q(|x|) , for 0.5 < x < 1.0 > + = pi - 2 Q(|x|) , for -1.0 < x < -0.5. */ > + float64x2_t y = vbslq_f64 (d->abs_mask, p, x); > + > + uint64x2_t is_neg = vcltzq_f64 (x); > + float64x2_t off = vreinterpretq_f64_u64 ( > + vandq_u64 (is_neg, vreinterpretq_u64_f64 (d->pi))); > + float64x2_t mul = vbslq_f64 (a_le_half, v_f64 (-1.0), v_f64 (2.0)); > + float64x2_t add = vbslq_f64 (a_le_half, d->pi_over_2, off); > + > + return vfmaq_f64 (add, mul, y); > +} > diff --git a/sysdeps/aarch64/fpu/acos_sve.c b/sysdeps/aarch64/fpu/acos_sve.c > new file mode 100644 > index 0000000000..1138a04e73 > --- /dev/null > +++ b/sysdeps/aarch64/fpu/acos_sve.c > @@ -0,0 +1,93 @@ > +/* Double-precision SVE inverse cos > + > + Copyright (C) 2023 Free Software Foundation, Inc. > + This file is part of the GNU C Library. > + > + The GNU C Library is free software; you can redistribute it and/or > + modify it under the terms of the GNU Lesser General Public > + License as published by the Free Software Foundation; either > + version 2.1 of the License, or (at your option) any later version. > + > + The GNU C Library is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + Lesser General Public License for more details. > + > + You should have received a copy of the GNU Lesser General Public > + License along with the GNU C Library; if not, see > + . */ > + > +#include "sv_math.h" > +#include "poly_sve_f64.h" > + > +static const struct data > +{ > + float64_t poly[12]; > + float64_t pi, pi_over_2; > +} data = { > + /* Polynomial approximation of (asin(sqrt(x)) - sqrt(x)) / (x * sqrt(x)) > + on [ 0x1p-106, 0x1p-2 ], relative error: 0x1.c3d8e169p-57. */ > + .poly = { 0x1.555555555554ep-3, 0x1.3333333337233p-4, 0x1.6db6db67f6d9fp-5, > + 0x1.f1c71fbd29fbbp-6, 0x1.6e8b264d467d6p-6, 0x1.1c5997c357e9dp-6, > + 0x1.c86a22cd9389dp-7, 0x1.856073c22ebbep-7, 0x1.fd1151acb6bedp-8, > + 0x1.087182f799c1dp-6, -0x1.6602748120927p-7, 0x1.cfa0dd1f9478p-6, }, > + .pi = 0x1.921fb54442d18p+1, > + .pi_over_2 = 0x1.921fb54442d18p+0, > +}; > + > +/* Double-precision SVE implementation of vector acos(x). > + > + For |x| in [0, 0.5], use an order 11 polynomial P such that the final > + approximation of asin is an odd polynomial: > + > + acos(x) ~ pi/2 - (x + x^3 P(x^2)). > + > + The largest observed error in this region is 1.18 ulps, > + _ZGVsMxv_acos (0x1.fbc5fe28ee9e3p-2) got 0x1.0d4d0f55667f6p+0 > + want 0x1.0d4d0f55667f7p+0. > + > + For |x| in [0.5, 1.0], use same approximation with a change of variable > + > + acos(x) = y + y * z * P(z), with z = (1-x)/2 and y = sqrt(z). > + > + The largest observed error in this region is 1.52 ulps, > + _ZGVsMxv_acos (0x1.24024271a500ap-1) got 0x1.ed82df4243f0dp-1 > + want 0x1.ed82df4243f0bp-1. */ > +svfloat64_t SV_NAME_D1 (acos) (svfloat64_t x, const svbool_t pg) > +{ > + const struct data *d = ptr_barrier (&data); > + > + svuint64_t sign = svand_x (pg, svreinterpret_u64 (x), 0x8000000000000000); > + svfloat64_t ax = svabs_x (pg, x); > + > + svbool_t a_gt_half = svacgt (pg, x, 0.5); > + > + /* Evaluate polynomial Q(x) = z + z * z2 * P(z2) with > + z2 = x ^ 2 and z = |x| , if |x| < 0.5 > + z2 = (1 - |x|) / 2 and z = sqrt(z2), if |x| >= 0.5. */ > + svfloat64_t z2 = svsel (a_gt_half, svmls_x (pg, sv_f64 (0.5), ax, 0.5), > + svmul_x (pg, x, x)); > + svfloat64_t z = svsqrt_m (ax, a_gt_half, z2); > + > + /* Use a single polynomial approximation P for both intervals. */ > + svfloat64_t z4 = svmul_x (pg, z2, z2); > + svfloat64_t z8 = svmul_x (pg, z4, z4); > + svfloat64_t z16 = svmul_x (pg, z8, z8); > + svfloat64_t p = sv_estrin_11_f64_x (pg, z2, z4, z8, z16, d->poly); > + > + /* Finalize polynomial: z + z * z2 * P(z2). */ > + p = svmla_x (pg, z, svmul_x (pg, z, z2), p); > + > + /* acos(|x|) = pi/2 - sign(x) * Q(|x|), for |x| < 0.5 > + = 2 Q(|x|) , for 0.5 < x < 1.0 > + = pi - 2 Q(|x|) , for -1.0 < x < -0.5. */ > + svfloat64_t y > + = svreinterpret_f64 (svorr_x (pg, svreinterpret_u64 (p), sign)); > + > + svbool_t is_neg = svcmplt (pg, x, 0.0); > + svfloat64_t off = svdup_f64_z (is_neg, d->pi); > + svfloat64_t mul = svsel (a_gt_half, sv_f64 (2.0), sv_f64 (-1.0)); > + svfloat64_t add = svsel (a_gt_half, off, sv_f64 (d->pi_over_2)); > + > + return svmla_x (pg, add, mul, y); > +} > diff --git a/sysdeps/aarch64/fpu/acosf_advsimd.c b/sysdeps/aarch64/fpu/acosf_advsimd.c > new file mode 100644 > index 0000000000..7d39e9b805 > --- /dev/null > +++ b/sysdeps/aarch64/fpu/acosf_advsimd.c > @@ -0,0 +1,113 @@ > +/* Single-precision AdvSIMD inverse cos > + > + Copyright (C) 2023 Free Software Foundation, Inc. > + This file is part of the GNU C Library. > + > + The GNU C Library is free software; you can redistribute it and/or > + modify it under the terms of the GNU Lesser General Public > + License as published by the Free Software Foundation; either > + version 2.1 of the License, or (at your option) any later version. > + > + The GNU C Library is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + Lesser General Public License for more details. > + > + You should have received a copy of the GNU Lesser General Public > + License along with the GNU C Library; if not, see > + . */ > + > +#include "v_math.h" > +#include "poly_advsimd_f32.h" > + > +static const struct data > +{ > + float32x4_t poly[5]; > + float32x4_t pi_over_2f, pif; > +} data = { > + /* Polynomial approximation of (asin(sqrt(x)) - sqrt(x)) / (x * sqrt(x)) on > + [ 0x1p-24 0x1p-2 ] order = 4 rel error: 0x1.00a23bbp-29 . */ > + .poly = { V4 (0x1.55555ep-3), V4 (0x1.33261ap-4), V4 (0x1.70d7dcp-5), > + V4 (0x1.b059dp-6), V4 (0x1.3af7d8p-5) }, > + .pi_over_2f = V4 (0x1.921fb6p+0f), > + .pif = V4 (0x1.921fb6p+1f), > +}; > + > +#define AbsMask 0x7fffffff > +#define Half 0x3f000000 > +#define One 0x3f800000 > +#define Small 0x32800000 /* 2^-26. */ > + > +#if WANT_SIMD_EXCEPT > +static float32x4_t VPCS_ATTR NOINLINE > +special_case (float32x4_t x, float32x4_t y, uint32x4_t special) > +{ > + return v_call_f32 (acosf, x, y, special); > +} > +#endif > + > +/* Single-precision implementation of vector acos(x). > + > + For |x| < Small, approximate acos(x) by pi/2 - x. Small = 2^-26 for correct > + rounding. > + If WANT_SIMD_EXCEPT = 0, Small = 0 and we proceed with the following > + approximation. > + > + For |x| in [Small, 0.5], use order 4 polynomial P such that the final > + approximation of asin is an odd polynomial: > + > + acos(x) ~ pi/2 - (x + x^3 P(x^2)). > + > + The largest observed error in this region is 1.26 ulps, > + _ZGVnN4v_acosf (0x1.843bfcp-2) got 0x1.2e934cp+0 want 0x1.2e934ap+0. > + > + For |x| in [0.5, 1.0], use same approximation with a change of variable > + > + acos(x) = y + y * z * P(z), with z = (1-x)/2 and y = sqrt(z). > + > + The largest observed error in this region is 1.32 ulps, > + _ZGVnN4v_acosf (0x1.15ba56p-1) got 0x1.feb33p-1 > + want 0x1.feb32ep-1. */ > +float32x4_t VPCS_ATTR V_NAME_F1 (acos) (float32x4_t x) > +{ > + const struct data *d = ptr_barrier (&data); > + > + uint32x4_t ix = vreinterpretq_u32_f32 (x); > + uint32x4_t ia = vandq_u32 (ix, v_u32 (AbsMask)); > + > +#if WANT_SIMD_EXCEPT > + /* A single comparison for One, Small and QNaN. */ > + uint32x4_t special > + = vcgtq_u32 (vsubq_u32 (ia, v_u32 (Small)), v_u32 (One - Small)); > + if (__glibc_unlikely (v_any_u32 (special))) > + return special_case (x, x, v_u32 (0xffffffff)); > +#endif > + > + float32x4_t ax = vreinterpretq_f32_u32 (ia); > + uint32x4_t a_le_half = vcleq_u32 (ia, v_u32 (Half)); > + > + /* Evaluate polynomial Q(x) = z + z * z2 * P(z2) with > + z2 = x ^ 2 and z = |x| , if |x| < 0.5 > + z2 = (1 - |x|) / 2 and z = sqrt(z2), if |x| >= 0.5. */ > + float32x4_t z2 = vbslq_f32 (a_le_half, vmulq_f32 (x, x), > + vfmsq_n_f32 (v_f32 (0.5), ax, 0.5)); > + float32x4_t z = vbslq_f32 (a_le_half, ax, vsqrtq_f32 (z2)); > + > + /* Use a single polynomial approximation P for both intervals. */ > + float32x4_t p = v_horner_4_f32 (z2, d->poly); > + /* Finalize polynomial: z + z * z2 * P(z2). */ > + p = vfmaq_f32 (z, vmulq_f32 (z, z2), p); > + > + /* acos(|x|) = pi/2 - sign(x) * Q(|x|), for |x| < 0.5 > + = 2 Q(|x|) , for 0.5 < x < 1.0 > + = pi - 2 Q(|x|) , for -1.0 < x < -0.5. */ > + float32x4_t y = vbslq_f32 (v_u32 (AbsMask), p, x); > + > + uint32x4_t is_neg = vcltzq_f32 (x); > + float32x4_t off = vreinterpretq_f32_u32 ( > + vandq_u32 (vreinterpretq_u32_f32 (d->pif), is_neg)); > + float32x4_t mul = vbslq_f32 (a_le_half, v_f32 (-1.0), v_f32 (2.0)); > + float32x4_t add = vbslq_f32 (a_le_half, d->pi_over_2f, off); > + > + return vfmaq_f32 (add, mul, y); > +} > diff --git a/sysdeps/aarch64/fpu/acosf_sve.c b/sysdeps/aarch64/fpu/acosf_sve.c > new file mode 100644 > index 0000000000..44253fa999 > --- /dev/null > +++ b/sysdeps/aarch64/fpu/acosf_sve.c > @@ -0,0 +1,86 @@ > +/* Single-precision SVE inverse cos > + > + Copyright (C) 2023 Free Software Foundation, Inc. > + This file is part of the GNU C Library. > + > + The GNU C Library is free software; you can redistribute it and/or > + modify it under the terms of the GNU Lesser General Public > + License as published by the Free Software Foundation; either > + version 2.1 of the License, or (at your option) any later version. > + > + The GNU C Library is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + Lesser General Public License for more details. > + > + You should have received a copy of the GNU Lesser General Public > + License along with the GNU C Library; if not, see > + . */ > + > +#include "sv_math.h" > +#include "poly_sve_f32.h" > + > +static const struct data > +{ > + float32_t poly[5]; > + float32_t pi, pi_over_2; > +} data = { > + /* Polynomial approximation of (asin(sqrt(x)) - sqrt(x)) / (x * sqrt(x)) on > + [ 0x1p-24 0x1p-2 ] order = 4 rel error: 0x1.00a23bbp-29 . */ > + .poly = { 0x1.55555ep-3, 0x1.33261ap-4, 0x1.70d7dcp-5, 0x1.b059dp-6, > + 0x1.3af7d8p-5, }, > + .pi = 0x1.921fb6p+1f, > + .pi_over_2 = 0x1.921fb6p+0f, > +}; > + > +/* Single-precision SVE implementation of vector acos(x). > + > + For |x| in [0, 0.5], use order 4 polynomial P such that the final > + approximation of asin is an odd polynomial: > + > + acos(x) ~ pi/2 - (x + x^3 P(x^2)). > + > + The largest observed error in this region is 1.16 ulps, > + _ZGVsMxv_acosf(0x1.ffbeccp-2) got 0x1.0c27f8p+0 > + want 0x1.0c27f6p+0. > + > + For |x| in [0.5, 1.0], use same approximation with a change of variable > + > + acos(x) = y + y * z * P(z), with z = (1-x)/2 and y = sqrt(z). > + > + The largest observed error in this region is 1.32 ulps, > + _ZGVsMxv_acosf (0x1.15ba56p-1) got 0x1.feb33p-1 > + want 0x1.feb32ep-1. */ > +svfloat32_t SV_NAME_F1 (acos) (svfloat32_t x, const svbool_t pg) > +{ > + const struct data *d = ptr_barrier (&data); > + > + svuint32_t sign = svand_x (pg, svreinterpret_u32 (x), 0x80000000); > + svfloat32_t ax = svabs_x (pg, x); > + svbool_t a_gt_half = svacgt (pg, x, 0.5); > + > + /* Evaluate polynomial Q(x) = z + z * z2 * P(z2) with > + z2 = x ^ 2 and z = |x| , if |x| < 0.5 > + z2 = (1 - |x|) / 2 and z = sqrt(z2), if |x| >= 0.5. */ > + svfloat32_t z2 = svsel (a_gt_half, svmls_x (pg, sv_f32 (0.5), ax, 0.5), > + svmul_x (pg, x, x)); > + svfloat32_t z = svsqrt_m (ax, a_gt_half, z2); > + > + /* Use a single polynomial approximation P for both intervals. */ > + svfloat32_t p = sv_horner_4_f32_x (pg, z2, d->poly); > + /* Finalize polynomial: z + z * z2 * P(z2). */ > + p = svmla_x (pg, z, svmul_x (pg, z, z2), p); > + > + /* acos(|x|) = pi/2 - sign(x) * Q(|x|), for |x| < 0.5 > + = 2 Q(|x|) , for 0.5 < x < 1.0 > + = pi - 2 Q(|x|) , for -1.0 < x < -0.5. */ > + svfloat32_t y > + = svreinterpret_f32 (svorr_x (pg, svreinterpret_u32 (p), sign)); > + > + svbool_t is_neg = svcmplt (pg, x, 0.0); > + svfloat32_t off = svdup_f32_z (is_neg, d->pi); > + svfloat32_t mul = svsel (a_gt_half, sv_f32 (2.0), sv_f32 (-1.0)); > + svfloat32_t add = svsel (a_gt_half, off, sv_f32 (d->pi_over_2)); > + > + return svmla_x (pg, add, mul, y); > +} > diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h > index 03778faf96..f313993d70 100644 > --- a/sysdeps/aarch64/fpu/bits/math-vector.h > +++ b/sysdeps/aarch64/fpu/bits/math-vector.h > @@ -49,6 +49,7 @@ typedef __SVBool_t __sv_bool_t; > > # define __vpcs __attribute__ ((__aarch64_vector_pcs__)) > > +__vpcs __f32x4_t _ZGVnN4v_acosf (__f32x4_t); > __vpcs __f32x4_t _ZGVnN4v_asinf (__f32x4_t); > __vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t); > __vpcs __f32x4_t _ZGVnN4v_expf (__f32x4_t); > @@ -60,6 +61,7 @@ __vpcs __f32x4_t _ZGVnN4v_log2f (__f32x4_t); > __vpcs __f32x4_t _ZGVnN4v_sinf (__f32x4_t); > __vpcs __f32x4_t _ZGVnN4v_tanf (__f32x4_t); > > +__vpcs __f64x2_t _ZGVnN2v_acos (__f64x2_t); > __vpcs __f64x2_t _ZGVnN2v_asin (__f64x2_t); > __vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t); > __vpcs __f64x2_t _ZGVnN2v_exp (__f64x2_t); > @@ -76,6 +78,7 @@ __vpcs __f64x2_t _ZGVnN2v_tan (__f64x2_t); > > #ifdef __SVE_VEC_MATH_SUPPORTED > > +__sv_f32_t _ZGVsMxv_acosf (__sv_f32_t, __sv_bool_t); > __sv_f32_t _ZGVsMxv_asinf (__sv_f32_t, __sv_bool_t); > __sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t); > __sv_f32_t _ZGVsMxv_expf (__sv_f32_t, __sv_bool_t); > @@ -87,6 +90,7 @@ __sv_f32_t _ZGVsMxv_log2f (__sv_f32_t, __sv_bool_t); > __sv_f32_t _ZGVsMxv_sinf (__sv_f32_t, __sv_bool_t); > __sv_f32_t _ZGVsMxv_tanf (__sv_f32_t, __sv_bool_t); > > +__sv_f64_t _ZGVsMxv_acos (__sv_f64_t, __sv_bool_t); > __sv_f64_t _ZGVsMxv_asin (__sv_f64_t, __sv_bool_t); > __sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t); > __sv_f64_t _ZGVsMxv_exp (__sv_f64_t, __sv_bool_t); > diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c > index b5ccd6b1cc..5a0cbf743b 100644 > --- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c > +++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c > @@ -23,6 +23,7 @@ > > #define VEC_TYPE float64x2_t > > +VPCS_VECTOR_WRAPPER (acos_advsimd, _ZGVnN2v_acos) > VPCS_VECTOR_WRAPPER (asin_advsimd, _ZGVnN2v_asin) > VPCS_VECTOR_WRAPPER (cos_advsimd, _ZGVnN2v_cos) > VPCS_VECTOR_WRAPPER (exp_advsimd, _ZGVnN2v_exp) > diff --git a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c > index fc3b20f421..bd89ff6133 100644 > --- a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c > +++ b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c > @@ -32,6 +32,7 @@ > return svlastb_f64 (svptrue_b64 (), mr); \ > } > > +SVE_VECTOR_WRAPPER (acos_sve, _ZGVsMxv_acos) > SVE_VECTOR_WRAPPER (asin_sve, _ZGVsMxv_asin) > SVE_VECTOR_WRAPPER (cos_sve, _ZGVsMxv_cos) > SVE_VECTOR_WRAPPER (exp_sve, _ZGVsMxv_exp) > diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c > index 0a36aa91f5..3fafca7557 100644 > --- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c > +++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c > @@ -23,6 +23,7 @@ > > #define VEC_TYPE float32x4_t > > +VPCS_VECTOR_WRAPPER (acosf_advsimd, _ZGVnN4v_acosf) > VPCS_VECTOR_WRAPPER (asinf_advsimd, _ZGVnN4v_asinf) > VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf) > VPCS_VECTOR_WRAPPER (expf_advsimd, _ZGVnN4v_expf) > diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c > index f7e4882c7a..b4ec9f777b 100644 > --- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c > +++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c > @@ -32,6 +32,7 @@ > return svlastb_f32 (svptrue_b32 (), mr); \ > } > > +SVE_VECTOR_WRAPPER (acosf_sve, _ZGVsMxv_acosf) > SVE_VECTOR_WRAPPER (asinf_sve, _ZGVsMxv_asinf) > SVE_VECTOR_WRAPPER (cosf_sve, _ZGVsMxv_cosf) > SVE_VECTOR_WRAPPER (expf_sve, _ZGVsMxv_expf) > diff --git a/sysdeps/aarch64/libm-test-ulps b/sysdeps/aarch64/libm-test-ulps > index 1edc0fc343..c2b6f21b9d 100644 > --- a/sysdeps/aarch64/libm-test-ulps > +++ b/sysdeps/aarch64/libm-test-ulps > @@ -6,11 +6,19 @@ double: 1 > float: 1 > ldouble: 1 > > +Function: "acos_advsimd": > +double: 1 > +float: 1 > + > Function: "acos_downward": > double: 1 > float: 1 > ldouble: 1 > > +Function: "acos_sve": > +double: 1 > +float: 1 > + > Function: "acos_towardzero": > double: 1 > float: 1 > diff --git a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist > index 6431c3fe65..f79eaaf241 100644 > --- a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist > +++ b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist > @@ -14,18 +14,22 @@ GLIBC_2.38 _ZGVsMxv_log F > GLIBC_2.38 _ZGVsMxv_logf F > GLIBC_2.38 _ZGVsMxv_sin F > GLIBC_2.38 _ZGVsMxv_sinf F > +GLIBC_2.39 _ZGVnN2v_acos F > GLIBC_2.39 _ZGVnN2v_asin F > GLIBC_2.39 _ZGVnN2v_exp10 F > GLIBC_2.39 _ZGVnN2v_exp2 F > GLIBC_2.39 _ZGVnN2v_log10 F > GLIBC_2.39 _ZGVnN2v_log2 F > GLIBC_2.39 _ZGVnN2v_tan F > +GLIBC_2.39 _ZGVnN4v_acosf F > GLIBC_2.39 _ZGVnN4v_asinf F > GLIBC_2.39 _ZGVnN4v_exp10f F > GLIBC_2.39 _ZGVnN4v_exp2f F > GLIBC_2.39 _ZGVnN4v_log10f F > GLIBC_2.39 _ZGVnN4v_log2f F > GLIBC_2.39 _ZGVnN4v_tanf F > +GLIBC_2.39 _ZGVsMxv_acos F > +GLIBC_2.39 _ZGVsMxv_acosf F > GLIBC_2.39 _ZGVsMxv_asin F > GLIBC_2.39 _ZGVsMxv_asinf F > GLIBC_2.39 _ZGVsMxv_exp10 F > -- > 2.27.0 >