From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2054.outbound.protection.outlook.com [40.107.6.54]) by sourceware.org (Postfix) with ESMTPS id 252D23858D32 for ; Fri, 10 Nov 2023 18:12:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 252D23858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 252D23858D32 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.6.54 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1699639931; cv=pass; b=vZoiCHbG2C7SCBS4nbOi6neetzxVn6bqR6iIInEBnfDn1oWsYJZwq/XeXFhzY5aulQK95D4EUHxAXLDYC5xMDTIEtupAHV7FuX24YwQGa6S32A3ZafPyl//3i6LTkS0orD7FvtWPDFbaAmUyrPT/8Kdvk23YK1xAaaXRPEV660g= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1699639931; c=relaxed/simple; bh=BsnaYaNl/xtzqLIQpaAhzR9wKjSw0pp725C2kpbtzZw=; h=DKIM-Signature:DKIM-Signature:Date:From:To:Subject:Message-ID: MIME-Version; b=q/XWnJMT0ToAprNfpdYdMZpcBzbwd75hjrZpJqzILhQQfF/FeMvr+rujx3EFMgvGUxAizp7WgoApbSh8nCB34LtJOJGXd8dXBFmCTqAzCeUvFs4hi5U/AzX/RJU+znEz9vD3FQwyq5JicgmvAfIl1K/WplNuZknkIwYaZNCWX20= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=i/BuzoDq45k9Hon3bQ3JP3FmfZYpI0TrxADNG3Si6MaeVmDq3BGS55DcK7K6ApMC8T2Jg6TYuKGDa8m2lUWaHtRTjNg6B8vsQNVRBI2emKwWlu5ZQKdzVSf8wGU18ELtBfryIBf7g8AlP711ftHn/IdF4WhPxu1fg//svcfQuYivbB4maPmnLVosQZW2nsU+4JlXK+Ch3G/GekSm+eop5jElbgMCttTDRUgLJjlsZUJIqYPoZUIkvK6KVKg7m8twrg+lN6YQTbhMjQEfFTUwuGBmGmqJKeZTmp/zm+7hbr7jwTjKKSpNQnqMcsf7ph3Z9L/g2D1BURrSpVyeo9wFNQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=x8s83BZWvvqVa441lPZALM/DnVd/zhRG1YZyE3BPbYU=; b=eLHS8J8hBBu07ErqA7hbN3VXGdD6gyNcqUrtmUAaV6OeRBRgtm4/R+3HBqid32jF3O9Fp94HCFgEWW9cN4BmItRRbnZUBzwpd8/xLvmF29+OUVWZuodGKok+79dsXzlLEx72StXhVwt7ZFHwd1oyUTGmSnKCPHy9ubvuC0ZQmW6P/u1IecROLOR5yAwfKsvBu+ZU5KHf+32AE4pDwX2XLQOmEUHnWAwdqt3iInFBVGQLyAyc616538G7wpfjZU1X1tWRa+pRncmfPGGPjIyU1YPUfDy85K+v5kGX4kgJ0TLOFebWf/iRZpm+I56MkINIeIhOXVhQz1UjW+fQPDJKyw== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=x8s83BZWvvqVa441lPZALM/DnVd/zhRG1YZyE3BPbYU=; b=Uyk1kVpYb85lcdQAiwzIdY59pZSdw+PpOu1TRn7M7YNy+ML82Fs+cse368MdKSJPm/haSWfkd+XO5ZFEpoCNFFIrQdd1mqCLvnQsRbjN6jG5HcvtdfQDXSN2c7+OdyrjjG8eX+rrie59hlBAVzO4DX8dDVq8UkKU1gA22KMoC60= Received: from DU2PR04CA0242.eurprd04.prod.outlook.com (2603:10a6:10:28e::7) by GV1PR08MB10401.eurprd08.prod.outlook.com (2603:10a6:150:170::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.28; Fri, 10 Nov 2023 18:12:04 +0000 Received: from DU6PEPF0000A7DE.eurprd02.prod.outlook.com (2603:10a6:10:28e:cafe::7d) by DU2PR04CA0242.outlook.office365.com (2603:10a6:10:28e::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.19 via Frontend Transport; Fri, 10 Nov 2023 18:12:03 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DU6PEPF0000A7DE.mail.protection.outlook.com (10.167.8.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.16 via Frontend Transport; Fri, 10 Nov 2023 18:12:03 +0000 Received: ("Tessian outbound 8289ea11ec17:v228"); Fri, 10 Nov 2023 18:12:03 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: da4ab405f649359b X-CR-MTA-TID: 64aa7808 Received: from aa2026604300.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id F1E03D56-DDF2-4D4C-B328-62D4133FC8F7.1; Fri, 10 Nov 2023 18:11:53 +0000 Received: from EUR03-DBA-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id aa2026604300.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 10 Nov 2023 18:11:53 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FylkIRaxyT+BU4L/NwK+xj3+l2ToF7HZPngjkW5twxFFheTifAF4dIKc3TNpbbw1a40T+K7MvG9tSJNqSlLPyHJStFIEexX98HqirZwDzw07/fMw2RQnp3b12OeXWyPkvsaFWztJI6FgvnFdVrGjaN0djjcBUYZawf4Aujo+TBGitvQOLa/mNxWHWiI1F+ZrniXGoVcNSVJRVVnsVelNSStPZp8kpv+0ZuyNDtQ1H0CyosmtgYcNqYm+XuR+LAWXOUQciCrZLg2cYq9ILnA1aIiJ7Jn27tg/u82TlUIJsg26B2PG21IxiJFpiPnQH3g7yTkW17UcmC236OzrCRTWqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=x8s83BZWvvqVa441lPZALM/DnVd/zhRG1YZyE3BPbYU=; b=ENM3ZC7ycI5QjkrOY4DzIvW65BD40Q5HaogBWC6lihtF9s7CvBQpcB9VLV8jLaL+qcbDHsIoVEuWqr14a8b9PcZm+yu4aeO0uJz4yUYRwZ/kwCJtSfVIvagmUlssONLlINTnya+5URXxP7vTKpdxl5BxlasJQ7UjMXOtdNhcwaaGNPLKzvAMAVtESTEN76xpCpvczFgg38ed+oZmli94J7DFYEnKIMGrbTEVdhd2+njyuoVtz3g8Mc6usvRORi+IVuNI3tXc4VkKqA7CjxPlw2+a4+FefuQcya30Yd6Gd71gAIJwsLEGKc1fK3leYQ+QBNchc6MOHrVX0VLL+U61Gg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=x8s83BZWvvqVa441lPZALM/DnVd/zhRG1YZyE3BPbYU=; b=Uyk1kVpYb85lcdQAiwzIdY59pZSdw+PpOu1TRn7M7YNy+ML82Fs+cse368MdKSJPm/haSWfkd+XO5ZFEpoCNFFIrQdd1mqCLvnQsRbjN6jG5HcvtdfQDXSN2c7+OdyrjjG8eX+rrie59hlBAVzO4DX8dDVq8UkKU1gA22KMoC60= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from DB9PR08MB7179.eurprd08.prod.outlook.com (2603:10a6:10:2cc::19) by PAXPR08MB7552.eurprd08.prod.outlook.com (2603:10a6:102:24f::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.19; Fri, 10 Nov 2023 18:11:50 +0000 Received: from DB9PR08MB7179.eurprd08.prod.outlook.com ([fe80::a991:ac53:e218:e554]) by DB9PR08MB7179.eurprd08.prod.outlook.com ([fe80::a991:ac53:e218:e554%3]) with mapi id 15.20.6954.029; Fri, 10 Nov 2023 18:11:50 +0000 Date: Fri, 10 Nov 2023 18:11:36 +0000 From: Szabolcs Nagy To: Joe Ramsay , Subject: Re: [PATCH 6/6] aarch64: Add vector implementations of expm1 routines Message-ID: References: <20231103121224.16835-1-Joe.Ramsay@arm.com> <20231103121224.16835-6-Joe.Ramsay@arm.com> Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20231103121224.16835-6-Joe.Ramsay@arm.com> X-ClientProxiedBy: LO2P265CA0416.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a0::20) To DB9PR08MB7179.eurprd08.prod.outlook.com (2603:10a6:10:2cc::19) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DB9PR08MB7179:EE_|PAXPR08MB7552:EE_|DU6PEPF0000A7DE:EE_|GV1PR08MB10401:EE_ X-MS-Office365-Filtering-Correlation-Id: cf462f27-6458-41d5-411e-08dbe2188aae x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: M85f7r4HSABzYoOyOGZBH81RH9rZhTcxzWqhvN2XDhC45bcGlVnPfi0GkGKzzNoVPWg2gDuaD/mTBeW9WvLp80gdlCRtBi+9tETyWzoIDxhu8WBW99QnTOHEjACUFHhUWKMUxyknwMcy32E96ARq7LIUVdRAi4hThoK1PHxznhnyOds5VbLP3XPckmrhmer/tiyz+U5Gd5w3K6I9wFLgPUr/QVwbw1+erPcG1PwzpIUu9eKxGV2K4YgHMQeODHEYhrFs7cF9X+5LosKm28bi3suxJonx91avVloEvtKpjP8faL5dbuMW61ULUMlgSPwBGpgKlKfqjwc3V22YNEL25qU373IgwI1A0dH5aCir93TfZ/NsstRc33brWDrwTrrmPf1yXJx4QkfWgT4Jv0LAfNr1ARBMJFgMu08HWF6TDc+j3GCB1/HOBX5701unKjLuJQ202QA6UWbTwWYvaxlqrCwxNHu3nqGEF+pTItO9x4kI5qgFaOQgtH7yzNTY2sj8LCnoDLerh2faRPRyrdlan0zOMygg/+TgC20MsEC+Z08s7MWDIvgQSYC9K7x0fMiYDxDiud5p5OUPxAVeXwXzlbSYKg582gCKfuxbZpWnjU7xZttgNLNmrdnJds4fOU7NfhOejQSaWWMES3uOnlPtLg== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DB9PR08MB7179.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(136003)(366004)(346002)(396003)(376002)(39860400002)(230922051799003)(451199024)(64100799003)(186009)(1800799009)(41300700001)(5660300002)(38100700002)(30864003)(86362001)(36756003)(2906002)(83380400001)(8676002)(8936002)(6506007)(2616005)(6486002)(66946007)(66476007)(66556008)(316002)(26005)(110136005)(44832011)(6512007)(478600001)(6666004)(2004002)(473944003)(357404004);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB7552 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DU6PEPF0000A7DE.eurprd02.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 14092324-aa33-49fc-a87a-08dbe21882ab X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0bY3esHFbig4ilF/RkICV6FUdsxQUfBuj+VxRRuvdpOE03t+G5Kz1iKSmaM/jQSHYoLImqUlKD5/iqfi9tXq57LAA5Z0wH1gIe58kCpI6Jjtp9TuRoKoydk1ME/jr6nRItYdwrb0nKW8WCLGud4Q2PrZv9zKO1WIK9PsBcOLk3Lypt3v0wOpEoCAnFW9txgbf1Q7+tDLL5D6YqxFffuUlfYgP9io+EHsRiEdsSBakRrOHwvO+Une0CgU4iusqlUiyWYaXYSviwVPsrDcsQPfCuM4SqjHSA3YvxXlsxY00VgWX6NISqC5QcRwBUFZfx3ZOrYVpg0US/J4XHdPpWD2ZYVQhXLSnsIBlgtbw/6PyTyZ7SX01SpKMqPrNlIsleYJYZwM+hGMSlmnVFxxZleyWUwwqyKW+Jg0jtnExJarFW4QiU11QnPOl+p9UTsXIcgKTkK0VDjEVd+fmZ0X+TKXYszhkkMlNr3EwpOKdgQeiCxo2V/ibzVNhlsIK9lAJZ/HluFq+YcrER/3QwBeX6vDZypPYKHU5ET3e3SgDFEi61jab5J3sL5wElVfI2r4YNwi8bL5kfkmQHaEwoguyaauACmcu40ZaBwin5uHFvp7PXZF0XU3EnjDckxFEKwwvUEW0v6mEX2tuxZa7kMGfAv1TpPmFhX4xrDG5E9c8GDkyZB1Twzd0DPug5D502YwZ4/g9uYdQbRyP9SjhhCemPbdi3TDTNPBByYUTdVqsk8HEvuUCiRkEyFBlJw6GGQm4g+KXmIH+oAjgYnMMDx0mI/GCNSvlLCT8GpBXS8SuUx2Gegh38ALsCt9CI0/W4Rsdegj X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(396003)(346002)(39860400002)(376002)(230922051799003)(186009)(64100799003)(82310400011)(451199024)(1800799009)(40470700004)(46966006)(36840700001)(8936002)(40480700001)(8676002)(41300700001)(2906002)(36756003)(5660300002)(36860700001)(6486002)(6512007)(86362001)(356005)(47076005)(81166007)(44832011)(30864003)(316002)(336012)(70586007)(26005)(40460700003)(83380400001)(70206006)(82740400003)(2616005)(110136005)(6666004)(478600001)(6506007)(2004002)(473944003)(357404004);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2023 18:12:03.6825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf462f27-6458-41d5-411e-08dbe2188aae X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000A7DE.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB10401 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The 11/03/2023 12:12, Joe Ramsay wrote: > --- please add the sign of zero test exception for expm1 mathvec test. > Thanks, > Joe > sysdeps/aarch64/fpu/Makefile | 1 + > sysdeps/aarch64/fpu/Versions | 4 + > sysdeps/aarch64/fpu/bits/math-vector.h | 4 + > sysdeps/aarch64/fpu/expm1_advsimd.c | 122 ++++++++++++++++++ > sysdeps/aarch64/fpu/expm1_sve.c | 99 ++++++++++++++ > sysdeps/aarch64/fpu/expm1f_advsimd.c | 117 +++++++++++++++++ > sysdeps/aarch64/fpu/expm1f_sve.c | 99 ++++++++++++++ > .../fpu/test-double-advsimd-wrappers.c | 1 + > .../aarch64/fpu/test-double-sve-wrappers.c | 1 + > .../aarch64/fpu/test-float-advsimd-wrappers.c | 1 + > sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 + > sysdeps/aarch64/libm-test-ulps | 8 ++ > .../unix/sysv/linux/aarch64/libmvec.abilist | 4 + > 13 files changed, 462 insertions(+) > create mode 100644 sysdeps/aarch64/fpu/expm1_advsimd.c > create mode 100644 sysdeps/aarch64/fpu/expm1_sve.c > create mode 100644 sysdeps/aarch64/fpu/expm1f_advsimd.c > create mode 100644 sysdeps/aarch64/fpu/expm1f_sve.c > > diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile > index c77c709edd..1fe4b52682 100644 > --- a/sysdeps/aarch64/fpu/Makefile > +++ b/sysdeps/aarch64/fpu/Makefile > @@ -6,6 +6,7 @@ libmvec-supported-funcs = acos \ > exp \ > exp10 \ > exp2 \ > + expm1 \ > log \ > log10 \ > log1p \ > diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions > index 2543649fbe..aaacacaebe 100644 > --- a/sysdeps/aarch64/fpu/Versions > +++ b/sysdeps/aarch64/fpu/Versions > @@ -42,6 +42,10 @@ libmvec { > _ZGVnN2v_exp2; > _ZGVsMxv_exp2f; > _ZGVsMxv_exp2; > + _ZGVnN4v_expm1f; > + _ZGVnN2v_expm1; > + _ZGVsMxv_expm1f; > + _ZGVsMxv_expm1; > _ZGVnN4v_log10f; > _ZGVnN2v_log10; > _ZGVsMxv_log10f; > diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h > index 51915cef22..52aad95e3b 100644 > --- a/sysdeps/aarch64/fpu/bits/math-vector.h > +++ b/sysdeps/aarch64/fpu/bits/math-vector.h > @@ -57,6 +57,7 @@ __vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t); > __vpcs __f32x4_t _ZGVnN4v_expf (__f32x4_t); > __vpcs __f32x4_t _ZGVnN4v_exp10f (__f32x4_t); > __vpcs __f32x4_t _ZGVnN4v_exp2f (__f32x4_t); > +__vpcs __f32x4_t _ZGVnN4v_expm1f (__f32x4_t); > __vpcs __f32x4_t _ZGVnN4v_logf (__f32x4_t); > __vpcs __f32x4_t _ZGVnN4v_log10f (__f32x4_t); > __vpcs __f32x4_t _ZGVnN4v_log1pf (__f32x4_t); > @@ -72,6 +73,7 @@ __vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t); > __vpcs __f64x2_t _ZGVnN2v_exp (__f64x2_t); > __vpcs __f64x2_t _ZGVnN2v_exp10 (__f64x2_t); > __vpcs __f64x2_t _ZGVnN2v_exp2 (__f64x2_t); > +__vpcs __f64x2_t _ZGVnN2v_expm1 (__f64x2_t); > __vpcs __f64x2_t _ZGVnN2v_log (__f64x2_t); > __vpcs __f64x2_t _ZGVnN2v_log10 (__f64x2_t); > __vpcs __f64x2_t _ZGVnN2v_log1p (__f64x2_t); > @@ -92,6 +94,7 @@ __sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t); > __sv_f32_t _ZGVsMxv_expf (__sv_f32_t, __sv_bool_t); > __sv_f32_t _ZGVsMxv_exp10f (__sv_f32_t, __sv_bool_t); > __sv_f32_t _ZGVsMxv_exp2f (__sv_f32_t, __sv_bool_t); > +__sv_f32_t _ZGVsMxv_expm1f (__sv_f32_t, __sv_bool_t); > __sv_f32_t _ZGVsMxv_logf (__sv_f32_t, __sv_bool_t); > __sv_f32_t _ZGVsMxv_log10f (__sv_f32_t, __sv_bool_t); > __sv_f32_t _ZGVsMxv_log1pf (__sv_f32_t, __sv_bool_t); > @@ -107,6 +110,7 @@ __sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t); > __sv_f64_t _ZGVsMxv_exp (__sv_f64_t, __sv_bool_t); > __sv_f64_t _ZGVsMxv_exp10 (__sv_f64_t, __sv_bool_t); > __sv_f64_t _ZGVsMxv_exp2 (__sv_f64_t, __sv_bool_t); > +__sv_f64_t _ZGVsMxv_expm1 (__sv_f64_t, __sv_bool_t); > __sv_f64_t _ZGVsMxv_log (__sv_f64_t, __sv_bool_t); > __sv_f64_t _ZGVsMxv_log10 (__sv_f64_t, __sv_bool_t); > __sv_f64_t _ZGVsMxv_log1p (__sv_f64_t, __sv_bool_t); > diff --git a/sysdeps/aarch64/fpu/expm1_advsimd.c b/sysdeps/aarch64/fpu/expm1_advsimd.c > new file mode 100644 > index 0000000000..a3aed8e35b > --- /dev/null > +++ b/sysdeps/aarch64/fpu/expm1_advsimd.c > @@ -0,0 +1,122 @@ > +/* Double-precision AdvSIMD expm1 > + > + Copyright (C) 2023 Free Software Foundation, Inc. > + This file is part of the GNU C Library. > + > + The GNU C Library is free software; you can redistribute it and/or > + modify it under the terms of the GNU Lesser General Public > + License as published by the Free Software Foundation; either > + version 2.1 of the License, or (at your option) any later version. > + > + The GNU C Library is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + Lesser General Public License for more details. > + > + You should have received a copy of the GNU Lesser General Public > + License along with the GNU C Library; if not, see > + . */ > + > +#include "v_math.h" > +#include "poly_advsimd_f64.h" > + > +static const struct data > +{ > + float64x2_t poly[11]; > + float64x2_t invln2, ln2_lo, ln2_hi, shift; > + int64x2_t exponent_bias; > +#if WANT_SIMD_EXCEPT > + uint64x2_t thresh, tiny_bound; > +#else > + float64x2_t oflow_bound; > +#endif > +} data = { > + /* Generated using fpminimax, with degree=12 in [log(2)/2, log(2)/2]. */ > + .poly = { V2 (0x1p-1), V2 (0x1.5555555555559p-3), V2 (0x1.555555555554bp-5), > + V2 (0x1.111111110f663p-7), V2 (0x1.6c16c16c1b5f3p-10), > + V2 (0x1.a01a01affa35dp-13), V2 (0x1.a01a018b4ecbbp-16), > + V2 (0x1.71ddf82db5bb4p-19), V2 (0x1.27e517fc0d54bp-22), > + V2 (0x1.af5eedae67435p-26), V2 (0x1.1f143d060a28ap-29) }, > + .invln2 = V2 (0x1.71547652b82fep0), > + .ln2_hi = V2 (0x1.62e42fefa39efp-1), > + .ln2_lo = V2 (0x1.abc9e3b39803fp-56), > + .shift = V2 (0x1.8p52), > + .exponent_bias = V2 (0x3ff0000000000000), > +#if WANT_SIMD_EXCEPT > + /* asuint64(oflow_bound) - asuint64(0x1p-51), shifted left by 1 for abs > + compare. */ > + .thresh = V2 (0x78c56fa6d34b552), > + /* asuint64(0x1p-51) << 1. */ > + .tiny_bound = V2 (0x3cc0000000000000 << 1), > +#else > + /* Value above which expm1(x) should overflow. Absolute value of the > + underflow bound is greater than this, so it catches both cases - there is > + a small window where fallbacks are triggered unnecessarily. */ > + .oflow_bound = V2 (0x1.62b7d369a5aa9p+9), > +#endif > +}; > + > +static float64x2_t VPCS_ATTR NOINLINE > +special_case (float64x2_t x, float64x2_t y, uint64x2_t special) > +{ > + return v_call_f64 (expm1, x, y, special); > +} > + > +/* Double-precision vector exp(x) - 1 function. > + The maximum error observed error is 2.18 ULP: > + _ZGVnN2v_expm1 (0x1.634ba0c237d7bp-2) got 0x1.a8b9ea8d66e22p-2 > + want 0x1.a8b9ea8d66e2p-2. */ > +float64x2_t VPCS_ATTR V_NAME_D1 (expm1) (float64x2_t x) > +{ > + const struct data *d = ptr_barrier (&data); > + > + uint64x2_t ix = vreinterpretq_u64_f64 (x); > + > +#if WANT_SIMD_EXCEPT > + /* If fp exceptions are to be triggered correctly, fall back to scalar for > + |x| < 2^-51, |x| > oflow_bound, Inf & NaN. Add ix to itself for > + shift-left by 1, and compare with thresh which was left-shifted offline - > + this is effectively an absolute compare. */ > + uint64x2_t special > + = vcgeq_u64 (vsubq_u64 (vaddq_u64 (ix, ix), d->tiny_bound), d->thresh); > + if (__glibc_unlikely (v_any_u64 (special))) > + x = v_zerofy_f64 (x, special); > +#else > + /* Large input, NaNs and Infs. */ > + uint64x2_t special = vceqzq_u64 (vcaltq_f64 (x, d->oflow_bound)); > +#endif > + > + /* Reduce argument to smaller range: > + Let i = round(x / ln2) > + and f = x - i * ln2, then f is in [-ln2/2, ln2/2]. > + exp(x) - 1 = 2^i * (expm1(f) + 1) - 1 > + where 2^i is exact because i is an integer. */ > + float64x2_t n = vsubq_f64 (vfmaq_f64 (d->shift, d->invln2, x), d->shift); > + int64x2_t i = vcvtq_s64_f64 (n); > + float64x2_t f = vfmsq_f64 (x, n, d->ln2_hi); > + f = vfmsq_f64 (f, n, d->ln2_lo); > + > + /* Approximate expm1(f) using polynomial. > + Taylor expansion for expm1(x) has the form: > + x + ax^2 + bx^3 + cx^4 .... > + So we calculate the polynomial P(f) = a + bf + cf^2 + ... > + and assemble the approximation expm1(f) ~= f + f^2 * P(f). */ > + float64x2_t f2 = vmulq_f64 (f, f); > + float64x2_t f4 = vmulq_f64 (f2, f2); > + float64x2_t f8 = vmulq_f64 (f4, f4); > + float64x2_t p = vfmaq_f64 (f, f2, v_estrin_10_f64 (f, f2, f4, f8, d->poly)); > + > + /* Assemble the result. > + expm1(x) ~= 2^i * (p + 1) - 1 > + Let t = 2^i. */ > + int64x2_t u = vaddq_s64 (vshlq_n_s64 (i, 52), d->exponent_bias); > + float64x2_t t = vreinterpretq_f64_s64 (u); > + > + if (__glibc_unlikely (v_any_u64 (special))) > + return special_case (vreinterpretq_f64_u64 (ix), > + vfmaq_f64 (vsubq_f64 (t, v_f64 (1.0)), p, t), > + special); > + > + /* expm1(x) ~= p * t + (t - 1). */ > + return vfmaq_f64 (vsubq_f64 (t, v_f64 (1.0)), p, t); > +} > diff --git a/sysdeps/aarch64/fpu/expm1_sve.c b/sysdeps/aarch64/fpu/expm1_sve.c > new file mode 100644 > index 0000000000..50646aff7c > --- /dev/null > +++ b/sysdeps/aarch64/fpu/expm1_sve.c > @@ -0,0 +1,99 @@ > +/* Double-precision SVE expm1 > + > + Copyright (C) 2023 Free Software Foundation, Inc. > + This file is part of the GNU C Library. > + > + The GNU C Library is free software; you can redistribute it and/or > + modify it under the terms of the GNU Lesser General Public > + License as published by the Free Software Foundation; either > + version 2.1 of the License, or (at your option) any later version. > + > + The GNU C Library is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + Lesser General Public License for more details. > + > + You should have received a copy of the GNU Lesser General Public > + License along with the GNU C Library; if not, see > + . */ > + > +#include "sv_math.h" > +#include "poly_sve_f64.h" > + > +#define SpecialBound 0x1.62b7d369a5aa9p+9 > +#define ExponentBias 0x3ff0000000000000 > + > +static const struct data > +{ > + double poly[11]; > + double shift, inv_ln2, special_bound; > + /* To be loaded in one quad-word. */ > + double ln2_hi, ln2_lo; > +} data = { > + /* Generated using fpminimax. */ > + .poly = { 0x1p-1, 0x1.5555555555559p-3, 0x1.555555555554bp-5, > + 0x1.111111110f663p-7, 0x1.6c16c16c1b5f3p-10, 0x1.a01a01affa35dp-13, > + 0x1.a01a018b4ecbbp-16, 0x1.71ddf82db5bb4p-19, 0x1.27e517fc0d54bp-22, > + 0x1.af5eedae67435p-26, 0x1.1f143d060a28ap-29, }, > + > + .special_bound = SpecialBound, > + .inv_ln2 = 0x1.71547652b82fep0, > + .ln2_hi = 0x1.62e42fefa39efp-1, > + .ln2_lo = 0x1.abc9e3b39803fp-56, > + .shift = 0x1.8p52, > +}; > + > +static svfloat64_t NOINLINE > +special_case (svfloat64_t x, svfloat64_t y, svbool_t pg) > +{ > + return sv_call_f64 (expm1, x, y, pg); > +} > + > +/* Double-precision vector exp(x) - 1 function. > + The maximum error observed error is 2.18 ULP: > + _ZGVsMxv_expm1(0x1.634ba0c237d7bp-2) got 0x1.a8b9ea8d66e22p-2 > + want 0x1.a8b9ea8d66e2p-2. */ > +svfloat64_t SV_NAME_D1 (expm1) (svfloat64_t x, svbool_t pg) > +{ > + const struct data *d = ptr_barrier (&data); > + > + /* Large, Nan/Inf. */ > + svbool_t special = svnot_z (pg, svaclt (pg, x, d->special_bound)); > + > + /* Reduce argument to smaller range: > + Let i = round(x / ln2) > + and f = x - i * ln2, then f is in [-ln2/2, ln2/2]. > + exp(x) - 1 = 2^i * (expm1(f) + 1) - 1 > + where 2^i is exact because i is an integer. */ > + svfloat64_t shift = sv_f64 (d->shift); > + svfloat64_t n = svsub_x (pg, svmla_x (pg, shift, x, d->inv_ln2), shift); > + svint64_t i = svcvt_s64_x (pg, n); > + svfloat64_t ln2 = svld1rq (svptrue_b64 (), &d->ln2_hi); > + svfloat64_t f = svmls_lane (x, n, ln2, 0); > + f = svmls_lane (f, n, ln2, 1); > + > + /* Approximate expm1(f) using polynomial. > + Taylor expansion for expm1(x) has the form: > + x + ax^2 + bx^3 + cx^4 .... > + So we calculate the polynomial P(f) = a + bf + cf^2 + ... > + and assemble the approximation expm1(f) ~= f + f^2 * P(f). */ > + svfloat64_t f2 = svmul_x (pg, f, f); > + svfloat64_t f4 = svmul_x (pg, f2, f2); > + svfloat64_t f8 = svmul_x (pg, f4, f4); > + svfloat64_t p > + = svmla_x (pg, f, f2, sv_estrin_10_f64_x (pg, f, f2, f4, f8, d->poly)); > + > + /* Assemble the result. > + expm1(x) ~= 2^i * (p + 1) - 1 > + Let t = 2^i. */ > + svint64_t u = svadd_x (pg, svlsl_x (pg, i, 52), ExponentBias); > + svfloat64_t t = svreinterpret_f64 (u); > + > + /* expm1(x) ~= p * t + (t - 1). */ > + svfloat64_t y = svmla_x (pg, svsub_x (pg, t, 1), p, t); > + > + if (__glibc_unlikely (svptest_any (pg, special))) > + return special_case (x, y, special); > + > + return y; > +} > diff --git a/sysdeps/aarch64/fpu/expm1f_advsimd.c b/sysdeps/aarch64/fpu/expm1f_advsimd.c > new file mode 100644 > index 0000000000..b27b75068a > --- /dev/null > +++ b/sysdeps/aarch64/fpu/expm1f_advsimd.c > @@ -0,0 +1,117 @@ > +/* Single-precision AdvSIMD expm1 > + > + Copyright (C) 2023 Free Software Foundation, Inc. > + This file is part of the GNU C Library. > + > + The GNU C Library is free software; you can redistribute it and/or > + modify it under the terms of the GNU Lesser General Public > + License as published by the Free Software Foundation; either > + version 2.1 of the License, or (at your option) any later version. > + > + The GNU C Library is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + Lesser General Public License for more details. > + > + You should have received a copy of the GNU Lesser General Public > + License along with the GNU C Library; if not, see > + . */ > + > +#include "v_math.h" > +#include "poly_advsimd_f32.h" > + > +static const struct data > +{ > + float32x4_t poly[5]; > + float32x4_t invln2, ln2_lo, ln2_hi, shift; > + int32x4_t exponent_bias; > +#if WANT_SIMD_EXCEPT > + uint32x4_t thresh; > +#else > + float32x4_t oflow_bound; > +#endif > +} data = { > + /* Generated using fpminimax with degree=5 in [-log(2)/2, log(2)/2]. */ > + .poly = { V4 (0x1.fffffep-2), V4 (0x1.5554aep-3), V4 (0x1.555736p-5), > + V4 (0x1.12287cp-7), V4 (0x1.6b55a2p-10) }, > + .invln2 = V4 (0x1.715476p+0f), > + .ln2_hi = V4 (0x1.62e4p-1f), > + .ln2_lo = V4 (0x1.7f7d1cp-20f), > + .shift = V4 (0x1.8p23f), > + .exponent_bias = V4 (0x3f800000), > +#if !WANT_SIMD_EXCEPT > + /* Value above which expm1f(x) should overflow. Absolute value of the > + underflow bound is greater than this, so it catches both cases - there is > + a small window where fallbacks are triggered unnecessarily. */ > + .oflow_bound = V4 (0x1.5ebc4p+6), > +#else > + /* asuint(oflow_bound) - asuint(0x1p-23), shifted left by 1 for absolute > + compare. */ > + .thresh = V4 (0x1d5ebc40), > +#endif > +}; > + > +/* asuint(0x1p-23), shifted by 1 for abs compare. */ > +#define TinyBound v_u32 (0x34000000 << 1) > + > +static float32x4_t VPCS_ATTR NOINLINE > +special_case (float32x4_t x, float32x4_t y, uint32x4_t special) > +{ > + return v_call_f32 (expm1f, x, y, special); > +} > + > +/* Single-precision vector exp(x) - 1 function. > + The maximum error is 1.51 ULP: > + _ZGVnN4v_expm1f (0x1.8baa96p-2) got 0x1.e2fb9p-2 > + want 0x1.e2fb94p-2. */ > +float32x4_t VPCS_ATTR V_NAME_F1 (expm1) (float32x4_t x) > +{ > + const struct data *d = ptr_barrier (&data); > + uint32x4_t ix = vreinterpretq_u32_f32 (x); > + > +#if WANT_SIMD_EXCEPT > + /* If fp exceptions are to be triggered correctly, fall back to scalar for > + |x| < 2^-23, |x| > oflow_bound, Inf & NaN. Add ix to itself for > + shift-left by 1, and compare with thresh which was left-shifted offline - > + this is effectively an absolute compare. */ > + uint32x4_t special > + = vcgeq_u32 (vsubq_u32 (vaddq_u32 (ix, ix), TinyBound), d->thresh); > + if (__glibc_unlikely (v_any_u32 (special))) > + x = v_zerofy_f32 (x, special); > +#else > + /* Handles very large values (+ve and -ve), +/-NaN, +/-Inf. */ > + uint32x4_t special = vceqzq_u32 (vcaltq_f32 (x, d->oflow_bound)); > +#endif > + > + /* Reduce argument to smaller range: > + Let i = round(x / ln2) > + and f = x - i * ln2, then f is in [-ln2/2, ln2/2]. > + exp(x) - 1 = 2^i * (expm1(f) + 1) - 1 > + where 2^i is exact because i is an integer. */ > + float32x4_t j = vsubq_f32 (vfmaq_f32 (d->shift, d->invln2, x), d->shift); > + int32x4_t i = vcvtq_s32_f32 (j); > + float32x4_t f = vfmsq_f32 (x, j, d->ln2_hi); > + f = vfmsq_f32 (f, j, d->ln2_lo); > + > + /* Approximate expm1(f) using polynomial. > + Taylor expansion for expm1(x) has the form: > + x + ax^2 + bx^3 + cx^4 .... > + So we calculate the polynomial P(f) = a + bf + cf^2 + ... > + and assemble the approximation expm1(f) ~= f + f^2 * P(f). */ > + float32x4_t p = v_horner_4_f32 (f, d->poly); > + p = vfmaq_f32 (f, vmulq_f32 (f, f), p); > + > + /* Assemble the result. > + expm1(x) ~= 2^i * (p + 1) - 1 > + Let t = 2^i. */ > + int32x4_t u = vaddq_s32 (vshlq_n_s32 (i, 23), d->exponent_bias); > + float32x4_t t = vreinterpretq_f32_s32 (u); > + > + if (__glibc_unlikely (v_any_u32 (special))) > + return special_case (vreinterpretq_f32_u32 (ix), > + vfmaq_f32 (vsubq_f32 (t, v_f32 (1.0f)), p, t), > + special); > + > + /* expm1(x) ~= p * t + (t - 1). */ > + return vfmaq_f32 (vsubq_f32 (t, v_f32 (1.0f)), p, t); > +} > diff --git a/sysdeps/aarch64/fpu/expm1f_sve.c b/sysdeps/aarch64/fpu/expm1f_sve.c > new file mode 100644 > index 0000000000..96e579e5b7 > --- /dev/null > +++ b/sysdeps/aarch64/fpu/expm1f_sve.c > @@ -0,0 +1,99 @@ > +/* Single-precision SVE expm1 > + > + Copyright (C) 2023 Free Software Foundation, Inc. > + This file is part of the GNU C Library. > + > + The GNU C Library is free software; you can redistribute it and/or > + modify it under the terms of the GNU Lesser General Public > + License as published by the Free Software Foundation; either > + version 2.1 of the License, or (at your option) any later version. > + > + The GNU C Library is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + Lesser General Public License for more details. > + > + You should have received a copy of the GNU Lesser General Public > + License along with the GNU C Library; if not, see > + . */ > + > +#include "sv_math.h" > +#include "poly_sve_f32.h" > + > +/* Largest value of x for which expm1(x) should round to -1. */ > +#define SpecialBound 0x1.5ebc4p+6f > + > +static const struct data > +{ > + /* These 4 are grouped together so they can be loaded as one quadword, then > + used with _lane forms of svmla/svmls. */ > + float c2, c4, ln2_hi, ln2_lo; > + float c0, c1, c3, inv_ln2, special_bound, shift; > +} data = { > + /* Generated using fpminimax. */ > + .c0 = 0x1.fffffep-2, .c1 = 0x1.5554aep-3, > + .c2 = 0x1.555736p-5, .c3 = 0x1.12287cp-7, > + .c4 = 0x1.6b55a2p-10, > + > + .special_bound = SpecialBound, .shift = 0x1.8p23f, > + .inv_ln2 = 0x1.715476p+0f, .ln2_hi = 0x1.62e4p-1f, > + .ln2_lo = 0x1.7f7d1cp-20f, > +}; > + > +#define C(i) sv_f32 (d->c##i) > + > +static svfloat32_t NOINLINE > +special_case (svfloat32_t x, svbool_t pg) > +{ > + return sv_call_f32 (expm1f, x, x, pg); > +} > + > +/* Single-precision SVE exp(x) - 1. Maximum error is 1.52 ULP: > + _ZGVsMxv_expm1f(0x1.8f4ebcp-2) got 0x1.e859dp-2 > + want 0x1.e859d4p-2. */ > +svfloat32_t SV_NAME_F1 (expm1) (svfloat32_t x, svbool_t pg) > +{ > + const struct data *d = ptr_barrier (&data); > + > + /* Large, NaN/Inf. */ > + svbool_t special = svnot_z (pg, svaclt (pg, x, d->special_bound)); > + > + if (__glibc_unlikely (svptest_any (pg, special))) > + return special_case (x, pg); > + > + /* This vector is reliant on layout of data - it contains constants > + that can be used with _lane forms of svmla/svmls. Values are: > + [ coeff_2, coeff_4, ln2_hi, ln2_lo ]. */ > + svfloat32_t lane_constants = svld1rq (svptrue_b32 (), &d->c2); > + > + /* Reduce argument to smaller range: > + Let i = round(x / ln2) > + and f = x - i * ln2, then f is in [-ln2/2, ln2/2]. > + exp(x) - 1 = 2^i * (expm1(f) + 1) - 1 > + where 2^i is exact because i is an integer. */ > + svfloat32_t j = svmla_x (pg, sv_f32 (d->shift), x, d->inv_ln2); > + j = svsub_x (pg, j, d->shift); > + svint32_t i = svcvt_s32_x (pg, j); > + > + svfloat32_t f = svmls_lane (x, j, lane_constants, 2); > + f = svmls_lane (f, j, lane_constants, 3); > + > + /* Approximate expm1(f) using polynomial. > + Taylor expansion for expm1(x) has the form: > + x + ax^2 + bx^3 + cx^4 .... > + So we calculate the polynomial P(f) = a + bf + cf^2 + ... > + and assemble the approximation expm1(f) ~= f + f^2 * P(f). */ > + svfloat32_t p12 = svmla_lane (C (1), f, lane_constants, 0); > + svfloat32_t p34 = svmla_lane (C (3), f, lane_constants, 1); > + svfloat32_t f2 = svmul_x (pg, f, f); > + svfloat32_t p = svmla_x (pg, p12, f2, p34); > + p = svmla_x (pg, C (0), f, p); > + p = svmla_x (pg, f, f2, p); > + > + /* Assemble the result. > + expm1(x) ~= 2^i * (p + 1) - 1 > + Let t = 2^i. */ > + svfloat32_t t = svreinterpret_f32 ( > + svadd_x (pg, svreinterpret_u32 (svlsl_x (pg, i, 23)), 0x3f800000)); > + return svmla_x (pg, svsub_x (pg, t, 1), p, t); > +} > diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c > index fc9e7aec47..bf495450d7 100644 > --- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c > +++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c > @@ -31,6 +31,7 @@ VPCS_VECTOR_WRAPPER (cos_advsimd, _ZGVnN2v_cos) > VPCS_VECTOR_WRAPPER (exp_advsimd, _ZGVnN2v_exp) > VPCS_VECTOR_WRAPPER (exp10_advsimd, _ZGVnN2v_exp10) > VPCS_VECTOR_WRAPPER (exp2_advsimd, _ZGVnN2v_exp2) > +VPCS_VECTOR_WRAPPER (expm1_advsimd, _ZGVnN2v_expm1) > VPCS_VECTOR_WRAPPER (log_advsimd, _ZGVnN2v_log) > VPCS_VECTOR_WRAPPER (log10_advsimd, _ZGVnN2v_log10) > VPCS_VECTOR_WRAPPER (log1p_advsimd, _ZGVnN2v_log1p) > diff --git a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c > index aea589d5fb..b5a627ad47 100644 > --- a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c > +++ b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c > @@ -50,6 +50,7 @@ SVE_VECTOR_WRAPPER (cos_sve, _ZGVsMxv_cos) > SVE_VECTOR_WRAPPER (exp_sve, _ZGVsMxv_exp) > SVE_VECTOR_WRAPPER (exp10_sve, _ZGVsMxv_exp10) > SVE_VECTOR_WRAPPER (exp2_sve, _ZGVsMxv_exp2) > +SVE_VECTOR_WRAPPER (expm1_sve, _ZGVsMxv_expm1) > SVE_VECTOR_WRAPPER (log_sve, _ZGVsMxv_log) > SVE_VECTOR_WRAPPER (log10_sve, _ZGVsMxv_log10) > SVE_VECTOR_WRAPPER (log1p_sve, _ZGVsMxv_log1p) > diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c > index 446fd7f538..26d9e98739 100644 > --- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c > +++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c > @@ -31,6 +31,7 @@ VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf) > VPCS_VECTOR_WRAPPER (expf_advsimd, _ZGVnN4v_expf) > VPCS_VECTOR_WRAPPER (exp10f_advsimd, _ZGVnN4v_exp10f) > VPCS_VECTOR_WRAPPER (exp2f_advsimd, _ZGVnN4v_exp2f) > +VPCS_VECTOR_WRAPPER (expm1f_advsimd, _ZGVnN4v_expm1f) > VPCS_VECTOR_WRAPPER (logf_advsimd, _ZGVnN4v_logf) > VPCS_VECTOR_WRAPPER (log10f_advsimd, _ZGVnN4v_log10f) > VPCS_VECTOR_WRAPPER (log1pf_advsimd, _ZGVnN4v_log1pf) > diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c > index ac17f60856..f286ee64c9 100644 > --- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c > +++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c > @@ -50,6 +50,7 @@ SVE_VECTOR_WRAPPER (cosf_sve, _ZGVsMxv_cosf) > SVE_VECTOR_WRAPPER (expf_sve, _ZGVsMxv_expf) > SVE_VECTOR_WRAPPER (exp10f_sve, _ZGVsMxv_exp10f) > SVE_VECTOR_WRAPPER (exp2f_sve, _ZGVsMxv_exp2f) > +SVE_VECTOR_WRAPPER (expm1f_sve, _ZGVsMxv_expm1f) > SVE_VECTOR_WRAPPER (logf_sve, _ZGVsMxv_logf) > SVE_VECTOR_WRAPPER (log10f_sve, _ZGVsMxv_log10f) > SVE_VECTOR_WRAPPER (log1pf_sve, _ZGVsMxv_log1pf) > diff --git a/sysdeps/aarch64/libm-test-ulps b/sysdeps/aarch64/libm-test-ulps > index a6b2f29a6f..1d52bf9ebf 100644 > --- a/sysdeps/aarch64/libm-test-ulps > +++ b/sysdeps/aarch64/libm-test-ulps > @@ -1078,11 +1078,19 @@ double: 1 > float: 1 > ldouble: 2 > > +Function: "expm1_advsimd": > +double: 2 > +float: 1 > + > Function: "expm1_downward": > double: 1 > float: 1 > ldouble: 2 > > +Function: "expm1_sve": > +double: 2 > +float: 1 > + > Function: "expm1_towardzero": > double: 1 > float: 2 > diff --git a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist > index 0f20b5be29..2bf4ea6332 100644 > --- a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist > +++ b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist > @@ -19,6 +19,7 @@ GLIBC_2.39 _ZGVnN2v_asin F > GLIBC_2.39 _ZGVnN2v_atan F > GLIBC_2.39 _ZGVnN2v_exp10 F > GLIBC_2.39 _ZGVnN2v_exp2 F > +GLIBC_2.39 _ZGVnN2v_expm1 F > GLIBC_2.39 _ZGVnN2v_log10 F > GLIBC_2.39 _ZGVnN2v_log1p F > GLIBC_2.39 _ZGVnN2v_log2 F > @@ -29,6 +30,7 @@ GLIBC_2.39 _ZGVnN4v_asinf F > GLIBC_2.39 _ZGVnN4v_atanf F > GLIBC_2.39 _ZGVnN4v_exp10f F > GLIBC_2.39 _ZGVnN4v_exp2f F > +GLIBC_2.39 _ZGVnN4v_expm1f F > GLIBC_2.39 _ZGVnN4v_log10f F > GLIBC_2.39 _ZGVnN4v_log1pf F > GLIBC_2.39 _ZGVnN4v_log2f F > @@ -44,6 +46,8 @@ GLIBC_2.39 _ZGVsMxv_exp10 F > GLIBC_2.39 _ZGVsMxv_exp10f F > GLIBC_2.39 _ZGVsMxv_exp2 F > GLIBC_2.39 _ZGVsMxv_exp2f F > +GLIBC_2.39 _ZGVsMxv_expm1 F > +GLIBC_2.39 _ZGVsMxv_expm1f F > GLIBC_2.39 _ZGVsMxv_log10 F > GLIBC_2.39 _ZGVsMxv_log10f F > GLIBC_2.39 _ZGVsMxv_log1p F > -- > 2.27.0 >