From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by sourceware.org (Postfix) with ESMTPS id BB3803858D1E for ; Mon, 25 Dec 2023 20:50:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BB3803858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=aurel32.net Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=aurel32.net ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BB3803858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:bc8:30d7:100::1 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703537448; cv=none; b=ggx+Fc7BuhVI3mYUc2x7AnxtMnVfDMhYS2m8lG+iCiwXmKm9hVtGJ4qF4SmNzDaFJCtx3zpYsHVb4+UKQHnX4divp47CDz7H4Y5FMO5tk1sEU/ywyVptvLQ+6yNYo75Vwkd4vqsgoKq29yG+86tI2KoqAlhVFP9OazwX8pED5l0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703537448; c=relaxed/simple; bh=AajlrS0UGkBR7ZbOhNycbNWBAVwJQfRg/uRdVbnizKg=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=KtbgI96163qeFipHhIBiu2+Spqse7X9m0r6sJOUXSMbMO/ecVTlDy5LyzRoDIqA7W50VsVw/2vQnNbAe9aggskqv3GPfcn1bDYEDENvOFoF2UbLUGREbG2fzqsVEs7+5iSP8rGDpDLvz9973U2M7aQ3BDYfwloqAGZgEZIXKrnE= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=In-Reply-To:Content-Type:MIME-Version:References: Message-ID:Subject:To:From:Date:Content-Transfer-Encoding:Cc:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=fRhsPmTQN+MURkWhI+laBnDE6XxnFbNJqkiM9G7HlbM=; b=de35HEMfGdlNddr1N/CRLylMCj 1l73zLVhpwZE1GliBJukJqjlxaSqEEAV+Bz8B4iAE8mqe0w2RrRzGnwoDAw5ypBxILARrqLUb0aDT 8Dzm3VbOIwNaX+2yzL0mI3FAcipdchbUfuHgOWU0Tqn27c19h7+1X/zH/57zKRd71eUg95ny/gysQ ONcZioZvq6hm7R/guUHcq9/9MuTm1ZnmtKfPJf2z+o33jirRjwOVACln4bafNouYGSaaEk4p2DIXR CM0e2RbUVKIHw7Q4ZEbmm1hJbFelODCftU0a5Ukfg1/I+hHxL2UnTWjnVmKX4qCADOqqXtld/Xj5K AzzlSInw==; Received: from ohm.aurel32.net ([2001:bc8:30d7:111::2] helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rHruO-0050su-A4; Mon, 25 Dec 2023 21:50:44 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.97) (envelope-from ) id 1rHruN-00000003PZs-1xDu; Mon, 25 Dec 2023 21:50:43 +0100 Date: Mon, 25 Dec 2023 21:50:43 +0100 From: Aurelien Jarno To: Palmer Dabbelt , libc-alpha@sourceware.org Subject: Re: [PATCH] RISC-V: Add support for dl_runtime_profile (BZ #31151) Message-ID: Mail-Followup-To: Palmer Dabbelt , libc-alpha@sourceware.org References: <20231215214447.4030756-1-aurelien@aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.12 (2023-09-09) X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 2023-12-21 00:25, Aurelien Jarno wrote: > On 2023-12-20 12:27, Palmer Dabbelt wrote: > > On Fri, 15 Dec 2023 13:44:47 PST (-0800), aurelien@aurel32.net wrote: > > > Code is mostly inspired from the LoongArch one, which has a similar ABI, > > > with minor changes to support riscv32 and register differences. > > > > > > This fixes elf/tst-sprof-basic. This also fixes elf/tst-audit1, > > > elf/tst-audit2 and elf/tst-audit8 with recent binutils snapshots when > > > --enable-bind-now is used. > > > > > > Resolves: BZ #31151 > > > --- > > > sysdeps/riscv/Makefile | 4 + > > > sysdeps/riscv/dl-link.sym | 18 ++++ > > > sysdeps/riscv/dl-machine.h | 27 +++++- > > > sysdeps/riscv/dl-trampoline.S | 177 ++++++++++++++++++++++++++++++++++ > > > 4 files changed, 225 insertions(+), 1 deletion(-) > > > create mode 100644 sysdeps/riscv/dl-link.sym > > > > > > diff --git a/sysdeps/riscv/Makefile b/sysdeps/riscv/Makefile > > > index 8fb10b164f..c08753ae8a 100644 > > > --- a/sysdeps/riscv/Makefile > > > +++ b/sysdeps/riscv/Makefile > > > @@ -2,6 +2,10 @@ ifeq ($(subdir),misc) > > > sysdep_headers += sys/asm.h > > > endif > > > > > > +ifeq ($(subdir),elf) > > > +gen-as-const-headers += dl-link.sym > > > +endif > > > + > > > # RISC-V's assembler also needs to know about PIC as it changes the definition > > > # of some assembler macros. > > > ASFLAGS-.os += $(pic-ccflag) > > > diff --git a/sysdeps/riscv/dl-link.sym b/sysdeps/riscv/dl-link.sym > > > new file mode 100644 > > > index 0000000000..b430a064c9 > > > --- /dev/null > > > +++ b/sysdeps/riscv/dl-link.sym > > > @@ -0,0 +1,18 @@ > > > +#include > > > +#include > > > +#include > > > + > > > +DL_SIZEOF_RG sizeof(struct La_riscv_regs) > > > +DL_SIZEOF_RV sizeof(struct La_riscv_retval) > > > + > > > +DL_OFFSET_RG_A0 offsetof(struct La_riscv_regs, lr_reg) > > > +#ifndef __riscv_float_abi_soft > > > +DL_OFFSET_RG_FA0 offsetof(struct La_riscv_regs, lr_fpreg) > > > +#endif > > > +DL_OFFSET_RG_RA offsetof(struct La_riscv_regs, lr_ra) > > > +DL_OFFSET_RG_SP offsetof(struct La_riscv_regs, lr_sp) > > > + > > > +DL_OFFSET_RV_A0 offsetof(struct La_riscv_retval, lrv_a0) > > > +#ifndef __riscv_float_abi_soft > > > +DL_OFFSET_RV_FA0 offsetof(struct La_riscv_retval, lrv_fa0) > > > +#endif > > > diff --git a/sysdeps/riscv/dl-machine.h b/sysdeps/riscv/dl-machine.h > > > index c0c9bd93ad..05bfa08da5 100644 > > > --- a/sysdeps/riscv/dl-machine.h > > > +++ b/sysdeps/riscv/dl-machine.h > > > @@ -313,13 +313,38 @@ elf_machine_runtime_setup (struct link_map *l, struct r_scope_elem *scope[], > > > if (l->l_info[DT_JMPREL]) > > > { > > > extern void _dl_runtime_resolve (void) __attribute__ ((visibility ("hidden"))); > > > + extern void _dl_runtime_profile (void) __attribute__ ((visibility ("hidden"))); > > > ElfW(Addr) *gotplt = (ElfW(Addr) *) D_PTR (l, l_info[DT_PLTGOT]); > > > /* If a library is prelinked but we have to relocate anyway, > > > we have to be able to undo the prelinking of .got.plt. > > > The prelinker saved the address of .plt for us here. */ > > > if (gotplt[1]) > > > l->l_mach.plt = gotplt[1] + l->l_addr; > > > - gotplt[0] = (ElfW(Addr)) &_dl_runtime_resolve; > > > + /* The got[0] entry contains the address of a function which gets > > > > At least "gotplt[0]", our names are different in here. > > Good catch, I fixed that locally. > > > That makes this almost exactly the same as the aarch64 port, except the > > index (which is 2 there, as it is in most ports). Presumably there's > > some ABI here, but I can't figure out why? > > I don't know the reason, but from what I understand it matches the > assembly code that binutils generates [1]. _dl_runtime_resolve is loaded > directly from the .got.plt address (ie at index 0). For instance, on > aarch64, it is loaded with an offset of 0x10, which corresponds to an > index of 2. > > [1] https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=bfd/elfnn-riscv.c;h=042266e791b453e7ef9b91153e29cc88e3f83a3f;hb=HEAD#l316 As pointed out by Andreas, this code from binutils matches the code from the Procedure Linkage Table section of the RISC-V ABIs Specification. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net