From: Siddhesh Poyarekar <siddhesh@gotplt.org>
To: Richard Henderson <rth@twiddle.net>, libc-alpha@sourceware.org
Cc: Marcus Shawcroft <marcus.shawcroft@arm.com>
Subject: Re: [PATCH 1/3] Guess L1 cache linesize for aarch64
Date: Fri, 09 Jun 2017 05:51:00 -0000 [thread overview]
Message-ID: <a86d5187-7536-fca0-ac61-259cb3d873e3@gotplt.org> (raw)
In-Reply-To: <20170608225728.26779-2-rth@twiddle.net>
On Friday 09 June 2017 04:27 AM, Richard Henderson wrote:
> Using the cache hierarchy linesize minimum in CTR_EL0.
> See the comment within the code for rationale.
>
> * sysdeps/unix/sysv/linux/aarch64/sysconf.c: New file.
>
Looks good to me.
Thanks,
Siddhesh
next prev parent reply other threads:[~2017-06-09 5:51 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-08 22:57 [PATCH 0/3] Add some missing cache infomation Richard Henderson
2017-06-08 22:57 ` [PATCH 2/3] Add hidden_proto for getauxval Richard Henderson
2017-06-09 5:55 ` Siddhesh Poyarekar
2017-06-09 6:58 ` Florian Weimer
2017-06-09 17:45 ` Richard Henderson
2017-06-09 17:49 ` Florian Weimer
2017-06-09 22:11 ` Richard Henderson
2017-06-08 22:57 ` [PATCH 1/3] Guess L1 cache linesize for aarch64 Richard Henderson
2017-06-09 5:51 ` Siddhesh Poyarekar [this message]
2017-06-09 5:52 ` Andrew Pinski
2017-10-10 7:24 ` Siddhesh Poyarekar
2017-10-10 10:20 ` Szabolcs Nagy
2017-10-10 10:37 ` Siddhesh Poyarekar
2017-10-10 11:01 ` Szabolcs Nagy
2017-10-10 11:56 ` Siddhesh Poyarekar
2017-10-10 14:20 ` Richard Henderson
2017-10-11 5:28 ` Siddhesh Poyarekar
2017-10-10 17:19 ` Szabolcs Nagy
2017-06-08 22:57 ` [PATCH 3/3] Add cache info for powerpc64 Richard Henderson
2017-06-09 6:59 ` Florian Weimer
2017-06-09 13:12 ` Tulio Magno Quites Machado Filho
2017-06-09 20:07 ` Richard Henderson
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