Re: [PATCH] powerpc: Move cache line size to rtld_global_ro

[Adhemerval Zanella <adhemerval.zanella@linaro.org>]

On 10/01/2020 13:09, Shawn Landden wrote:
> Not trying to say anything stupid, but why can't we just detect the cache line size using the "dcbz" instruction, as documented in the PowerISA document? It is because the ancient G5 also has a "dcbzl" instruction that clears a wider size (the actually cache line size)?
> 

AFAIK you can't detect the data cache block size using the dcbz instruction,
in fact PowerISA 3.0B states that this information should be provided by the
operation system (Book II, Chapter 4.1 Parameters Useful to Application
Programs).

Linux provided it by AT_DCACHEBSIZE field in auxv and it is implemented in the
kernel by a pre-defined table (arch/powerpc/kernel/cputable.c). This is how
glibc obtain such information (sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c).

The issue I pointed out is for static binaries that dlopen a shared library,
mem* calls done by the library (which will call the loaded libc.so one) won't
see the field properly initialized. Some architectures fix rtld initialization
by reimplementing the _dl_static_init.  It looks up for the '_dl_var_init' and
calls it, taking care of relro segments by unmap/mmap the segment.

And the dcbzl seems to be a hack pushed by Apple for some reason, which should
not be required on Linux:

"dcbz" only operates on 32 bytes when the special HID5 compatiblity bit that 
apple added to the 970 is set. This is _NOT_ the normal case and this bit isn't 
set in linux unless you explicitely set it by modifying the kernel [1]." 

[1] https://lists.ozlabs.org/pipermail/linuxppc64-dev/2004-March/001383.html