From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from va-1-15.ptr.blmpb.com (va-1-15.ptr.blmpb.com [209.127.230.15]) by sourceware.org (Postfix) with ESMTPS id B58B33858408 for ; Tue, 2 Jan 2024 09:43:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B58B33858408 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B58B33858408 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=209.127.230.15 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704188597; cv=none; b=ngUAMqhZJ81nkTvVeHdHzNBJkslZrkdkorL96UdBCBgHFqvfimOPyfyxexYBjvTTU3lKKMJVE0XdhefkYlJLo4iKAMsyreiXAdavbwltnpUY7FaCA0SkUmO46g2rv65VtAUwVLY5RCk5Lge/PaYXufsIN3lWTCuyw6srw7+RTjg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704188597; c=relaxed/simple; bh=kbYYFf3bEJBe6ydJ+UASN4a9r2+XT0IwFtnhVfJ6t0w=; h=DKIM-Signature:From:Subject:Date:Message-Id:Mime-Version:To; b=LlVbGE3wJ7ofKB4UHKHtenTV0rvL96z10SFWt7oZVegtbBtwraa0NYhcjkNf3+OA833qrhH2LVJcD+kWdBM/i4Uk/9+t+J4Qyzm2+hosvFSIZyZuev+A6fZhd0vEKCfMAyHKKuUCfVjEZIDatDRZWDnBF4zu1a1e6z0DBAeLA4U= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1704188587; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=btrbVZ6SGucuYH00ojLVyjHWP0dJ+zG1u7/yKudlXKg=; b=g2k3WYqQgiW/wzzNvGjZQ1JQeXW4qK5NUCFVnN16LNx87KMpNFqbYAwO6VaSzNaRPPe9Yd K7C1cfq42UALetaicU1UqQuvUuzJM6fxaWAqXcepnp0rBIpuexrgvN8VlVf+RmkxKGMtun sCbrdocROidRJrNhSd4AD+uGswKoONHeFw9ntVLkGuto1qjrYQRlfTvuy9h/5E77gjr3Cc UTsb0jnZ4ikePl1vJtVJ7sckvN8UI0qTTjpJ1aM58TP8y+dWyAyJj5z7d8vmNPwXq4JbqJ czCkyALmKAVfyrWzo5GoCzcX7s+Ka3ZH68Dt3IkDzDlZO2l3eTB7Hkp3nHo6pg== From: "Junxian Zhu" Subject: Re: [PATCH 2/2] MIPS: Hard-float rounding instructions support Date: Tue, 2 Jan 2024 17:43:04 +0800 In-Reply-To: X-Original-From: Junxian Zhu Cc: User-Agent: Mozilla Thunderbird Content-Transfer-Encoding: quoted-printable X-Lms-Return-Path: Message-Id: Mime-Version: 1.0 References: <20231225103548.1615-2-zhujunxian@oss.cipunited.com> <20231225103548.1615-4-zhujunxian@oss.cipunited.com> Content-Type: text/plain; charset=UTF-8 Received: from [192.168.8.110] ([171.15.158.108]) by smtp.feishu.cn with ESMTPS; Tue, 02 Jan 2024 17:43:05 +0800 To: "Xi Ruoyao" X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: =E5=9C=A8 2023/12/26 16:29, Xi Ruoyao =E5=86=99=E9=81=93: > On Tue, 2023-12-26 at 10:37 +0800, Junxian Zhu wrote: >> =E5=9C=A8 2023/12/25 18:51, Xi Ruoyao =E5=86=99=E9=81=93: >>> On Mon, 2023-12-25 at 18:35 +0800, Junxian Zhu wrote: >>> >>> /* snip */ >>> >>>> +/* >>>> + * ceil(x) >>>> + * Return x rounded toward -inf to integral value >>>> + * Method: >>>> + * Bit twiddling. >>>> + */ >>>> + >>>> +#if ((__mips_fpr =3D=3D 64) && (__mips_hard_float =3D=3D 1) && ((__mi= ps =3D=3D 32 && __mips_isa_rev > 1) || __mips =3D=3D 64)) >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +ENTRY(__ceil) >>>> + .set push >>>> + .set noreorder >>>> + .set noat >>>> +# $f0=3Dret, $f12=3Ddouble, a0=3Dint64/int32_h, a1=3Dint32_l, a2=3Dsi= gn, a3=3Dexp >>>> +#if __mips =3D=3D 64 >>>> + dmfc1=C2=A0=C2=A0 a0, $f12 # assign int64 >>>> +#else >>>> + mfhc1=C2=A0=C2=A0 a0, $f12 # assign int64 >>>> +#endif >>>> + cfc1=C2=A0=C2=A0=C2=A0 t0, $f26 >>>> + ceil.l.d=C2=A0=C2=A0=C2=A0 $f0, $f12 >>> No, C23 does not allow this function to raise an INEXACT exception, but >>> ceil.l.d will do so. >>> >>> Such optimizations should be performed in GCC which can be controlled b= y >>> the programmer with -std=3Dc23 and/or -f[no-]fp-int-builtin-inexact, no= t >>> in Glibc where we cannot know if the programmer wants to deviate from >>> C23. >> The cfc1 instruction will backup float point exception status before >> running ceil.l.d, and the following ctc1 will restore float point >> exception status to avoid INEXACT exception raised by ceil.l.d. It's the >> same way like what have been done in s_ceil.S for i386. > Still incorrect because when the Enable field of FCSR contains INEXACT a > SIGFPE will be immediately delivered and there is no way to recover. A > demonstration: > > #define _GNU_SOURCE > #include > #include > > int main() > { > printf("%d\n", feenableexcept(FE_INEXACT)); > > double data =3D 114.514; > long control; > asm("cfc1\t%1,$f26\n\t" > "ceil.l.d\t%0,%0\n\t" > "cvt.d.l\t%0,%0\n\t" > "ctc1\t%1,$f26": "+f"(data), "=3Dr"(control)); > printf("%.15f\n", data); > return 0; > } > > On i386 the fnstenv instruction also masks out all the FP exceptions so > this is not a problem. See commit 26b0bf96000a. I can use "ctc1 $0, $28" to disable all float point exception to ensure=20 no FP exceptions occur at here. But it will introduce additional=20 consumption.