From: Joseph Myers <joseph@codesourcery.com>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: <libc-alpha@sourceware.org>, <patches@groups.riscv.org>,
Andrew Waterman <andrew@sifive.com>, <dj@redhat.com>,
Darius Rad <darius@bluespec.com>
Subject: Re: [PATCH v6 15/16] RISC-V: Build Infastructure
Date: Fri, 26 Jan 2018 13:15:00 -0000 [thread overview]
Message-ID: <alpine.DEB.2.20.1801261233390.14878@digraph.polyomino.org.uk> (raw)
In-Reply-To: <20180126054443.22702-16-palmer@dabbelt.com>
On Thu, 25 Jan 2018, Palmer Dabbelt wrote:
> diff --git a/sysdeps/unix/sysv/linux/riscv/Makefile b/sysdeps/unix/sysv/linux/riscv/Makefile
> +abi-variants := ilp32 ilp32d lp64 lp64d
Cut this down to the two supported variants.
> +abi-ilp32-condition := !defined __LP64__ && defined __riscv_float_abi_soft
> +abi-ilp32d-condition := !defined __LP64__ && defined __riscv_float_abi_double
Likewise, remove these as not needed until RV32 is supported.
> diff --git a/sysdeps/unix/sysv/linux/riscv/shlib-versions b/sysdeps/unix/sysv/linux/riscv/shlib-versions
> new file mode 100644
> index 000000000000..1d2561e7a8ec
> --- /dev/null
> +++ b/sysdeps/unix/sysv/linux/riscv/shlib-versions
> @@ -0,0 +1,13 @@
> +DEFAULT GLIBC_2.27
> +
> +%if RISCV_ABI_XLEN == 64 && RISCV_ABI_FLEN == 64
> +ld=ld-linux-riscv64-lp64d.so.1
> +%elif RISCV_ABI_XLEN == 64 && RISCV_ABI_FLEN == 0
> +ld=ld-linux-riscv64-lp64.so.1
> +%elif RISCV_ABI_XLEN == 32 && RISCV_ABI_FLEN == 64
> +ld=ld-linux-riscv32-ilp32d.so.1
> +%elif RISCV_ABI_XLEN == 32 && RISCV_ABI_FLEN == 0
> +ld=ld-linux-riscv32-ilp32.so.1
And remove the 32-bit ABIs here.
--
Joseph S. Myers
joseph@codesourcery.com
next prev parent reply other threads:[~2018-01-26 12:37 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-26 5:44 RISC-V glibc port, v6 Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 10/16] RISC-V: Atomic and Locking Routines Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 01/16] sysdeps/init_array: Add PREINIT_FUNCTION to crti.S Palmer Dabbelt
2018-01-26 12:56 ` Joseph Myers
2018-01-26 17:54 ` Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 16/16] Add RISC-V to build-many-glibcs.py Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 04/16] Add documentation for __riscv_flush_icache Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 15/16] RISC-V: Build Infastructure Palmer Dabbelt
2018-01-26 13:15 ` Joseph Myers [this message]
2018-01-26 18:00 ` Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 12/16] RISC-V: Linux ABI Palmer Dabbelt
2018-01-26 13:12 ` Joseph Myers
2018-01-26 18:05 ` Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 06/16] RISC-V: Startup and Dynamic Loading Code Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 02/16] Skeleton documentation for the RISC-V port Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 11/16] RISC-V: Linux Syscall Interface Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 03/16] Add RISC-V entries to config.h.in Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 05/16] RISC-V: ABI Implementation Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 08/16] RISC-V: Generic <math.h> and soft-fp Routines Palmer Dabbelt
2018-01-26 13:10 ` Joseph Myers
2018-01-26 18:03 ` Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 14/16] RISC-V: Add ABI Lists Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 07/16] RISC-V: Thread-Local Storage Support Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 09/16] RISC-V: Hard Float Support Palmer Dabbelt
2018-01-26 5:45 ` [PATCH v6 13/16] RISC-V: Linux Startup and Dynamic Loading Code Palmer Dabbelt
2018-01-26 12:49 ` RISC-V glibc port, v6 Joseph Myers
2018-01-26 17:51 ` Palmer Dabbelt
2018-01-26 15:05 ` Joseph Myers
2018-01-26 18:18 ` Palmer Dabbelt
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