From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from esa3.mentor.iphmx.com (esa3.mentor.iphmx.com [68.232.137.180]) by sourceware.org (Postfix) with ESMTPS id 220CD3851C22; Thu, 4 Jun 2020 22:08:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 220CD3851C22 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=joseph_myers@mentor.com IronPort-SDR: AfjViObP0JWAzCWR126UcwVOEFvMoECmV9jyOCkecDFTwK3YeCjvN4rlIYnTprxdYWsApERS0P U/GsqP/YXck2/z/lsLOmLjBwd7fXU4ACFXwiHJK86TxvXuipOy1lE1MZRz2qPpRvb33tcW2AXt eKdK8VQtxNqvU5Du4PDVLCsilArgU9mTiO6yQq/FKHsjB+aWdJrDoFT5yvXjx0hpZqkRKLqyHf 8dfKrh0s7Lmq6T2X07bOOAsjIQIvEiZVbcusJJ9PW+OKrwy1G51LuKhVjuoyE+3dTo/BPvUiJX abw= X-IronPort-AV: E=Sophos;i="5.73,472,1583222400"; d="scan'208";a="49526647" Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa3.mentor.iphmx.com with ESMTP; 04 Jun 2020 14:08:09 -0800 IronPort-SDR: 10Lvn9hMbIgp6Wmv7tGgT/Bb+RFvig0/R1k1fveX5H7Yt2roTj6zgGCC1dp89r/XljPZBd6TNV Ylfgb2UMBeVoR3WYnwLk6A5YcMdvGzOClszLxWzKYwoHZ31s2/E4yimjtKTnS8vuBk5kl4vy9K 41mPdkl1eZFrKFmSEkxp1shYieeZTiKGLjQT+TBX3Tkz2E+OQ9inB98+0gnco8Zd+0wNmY9dG5 9c4hFdi3/PO+MQK8TUxIjjpcOkxbLfry5T4klJZULKuE+xlfW9/xN+eEkrHml9nS1RolhNufrv VCo= Date: Thu, 4 Jun 2020 22:08:02 +0000 From: Joseph Myers X-X-Sender: jsm28@digraph.polyomino.org.uk To: Daniel Kolesa CC: Segher Boessenkool , , Rich Felker , =?ISO-8859-15?Q?Michal_Such=E1nek?= , , , Will Springer , Palmer Dabbelt via binutils , via libc-dev , Subject: Re: [musl] Re: ppc64le and 32-bit LE userland compatibility In-Reply-To: <60fa8bd7-2439-4403-a0eb-166a2fb49a4b@www.fastmail.com> Message-ID: References: <20200602142337.GS25173@kitsune.suse.cz> <3aeb6dfe-ae23-42f9-ac23-16be6b54a850@www.fastmail.com> <20200604171232.GG31009@gate.crashing.org> <20200604171844.GO1079@brightrain.aerifal.cx> <20200604173312.GI31009@gate.crashing.org> <20200604211009.GK31009@gate.crashing.org> <60fa8bd7-2439-4403-a0eb-166a2fb49a4b@www.fastmail.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-06.mgc.mentorg.com (139.181.222.6) To svr-ies-mbx-02.mgc.mentorg.com (139.181.222.2) X-Spam-Status: No, score=-3130.9 required=5.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Jun 2020 22:08:11 -0000 On Thu, 4 Jun 2020, Daniel Kolesa wrote: > The ELFv2 document specifies things like passing of quadruple precision > floats. Indeed, VSX is needed there, but that's not a concern if you > *don't* use quadruple precision floats. My understanding is that the registers used for argument passing are all ones that exactly correspond to the Vector registers in earlier instruction set versions. In other words, you could *in principle* produce an object, or a whole libm shared library, that (a) passes or receives _Float128 values in registers, (b) does not use any instructions beyond those available with -mcpu=970, (c) would work as intended whether executed on a 970 or on POWER8 and (d) when executed on POWER8, would fully interoperate with objects receiving or passing _Float128 values and compiled for POWER8 to use VSX instructions for that purpose. GCC may not support _Float128 for older processors, but that doesn't prevent you from maintaining patches to add such support. (But if you want to support those 64-bit processors that don't have Vector registers at all, you indeed can't use binary128 and interoperate with code using VSX for that format in POWER8.) (Cf. how the Arm hard-float ABI variant works even on processors with single-precision-only VFP, because such processors still have the double-precision loads and stores although not double-precision arithmetic. When working on that ABI support in GCC some years ago, I also made sure that GNU vector types corresponding to NEON vector types were passed consistently for the hard-float ABI whether or not any vector instructions were present - thus, avoiding depending on the machine modes for those vector types because GCC could choose a different machine mode depending on the instructions available.) -- Joseph S. Myers joseph@codesourcery.com