From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from esa4.hgst.iphmx.com (esa4.hgst.iphmx.com [216.71.154.42]) by sourceware.org (Postfix) with ESMTPS id 4E3373857C40 for ; Sat, 11 Jul 2020 22:14:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 4E3373857C40 IronPort-SDR: 2Z48quYqobNrxD5kB1NN8EjOrnWDDZt7GYuXov/JxSxTU5xvRn5SCT22rKxwRnOwTrh5iAeXp+ 83hpca3k4m6FR/LaJmtkDUQGwm2zU3jVkiCowgYA4owS7KQfyuRBu6+9SYAKHgvT4dh60XLvT6 76HKc4XGX3+clNWU2BEZ1g7AX4mHn93BfFIqwM6ClzBo0vKjM97dowV/CNRs+Wtyh1n0rs2soK ZN4g6lGaa+e5Cla1b9JKFkyutHZoX+LyxWi2n6KkNZiekTOXAsvSx6e6zp2y02pVbXpbT6EzQ0 gpE= X-IronPort-AV: E=Sophos;i="5.75,341,1589212800"; d="scan'208";a="142220833" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 12 Jul 2020 06:14:03 +0800 IronPort-SDR: 6zasmIEk+pqeyle9FOtPzbEIsLMOUIBJ56MMLB8SgyYg31CluxsNe0QHnzR4eARy8Wj6/cLhjg LZF0CeGl+gop72xf+FmvEEABmK2nYRtfg= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2020 15:02:35 -0700 IronPort-SDR: 55OmbBCvaCR7P0/qBlmOyljwLrTUvxqPvOxIg+lTL9Yu/CTR582o10Yj5/+ixg/xPJDdj6qKVA YseexHJAs69Q== WDCIronportException: Internal Received: from unknown (HELO redsun52) ([10.149.66.28]) by uls-op-cesaip02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2020 15:14:02 -0700 Date: Sat, 11 Jul 2020 23:13:58 +0100 (BST) From: "Maciej W. Rozycki" To: Alistair Francis cc: Alistair Francis , GNU C Library Subject: Re: [PATCH v2 10/18] RISC-V: Hard float support for 32-bit In-Reply-To: Message-ID: References: User-Agent: Alpine 2.21 (LFD 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 11 Jul 2020 22:14:05 -0000 On Sat, 11 Jul 2020, Alistair Francis wrote: > > Shouldn't we also move the XLEN-agnostic optimised functions to > > `sysdeps/riscv/rv{f,d}/' with this change? I think we only need to keep > > those that use the `long int' type at the interface in the XLEN-specific > > directory. > > They are all xlen dependent though. All of the 64-bit ones use > fcvt.l.d (or something similar) which doesn't exist on RV32. Umm, right, I missed this detail, sorry for the confusion. > Although the functions end up being the same, the actual assembly > instruction called is different. We can look at consolidating them > into a single file and do a xlen/__WORDSIZE macro check. I don't think there is a simple alternative available for RV32 that would be worth keeping together with the RV64 variant. Did I miss anything? What instruction(s) do you have in mind? > At this stage in glibc development I don't really want to change the > floating point helpers. Can we leave this as is and then for the next > release I can consolidate all of these into single files that do > xlen/__WORDSIZE #ifdefs? That way we will just have a single file (for > each operation) for RISC-V that will call a different assembly > instruction based on xlen or __WORDSIZE. Sure, in these circumstances this change is fine with me then. Maciej