From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from va-2-32.ptr.blmpb.com (va-2-32.ptr.blmpb.com [209.127.231.32]) by sourceware.org (Postfix) with ESMTPS id BC3113858413 for ; Tue, 2 Jan 2024 10:08:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BC3113858413 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BC3113858413 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=209.127.231.32 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704190109; cv=none; b=ddmFxbP5Isy3jBy7NaFIgdc05tqWv2MnG5che8hya+o7cD6kQ4W8+as3gbnABqK5bQJj+BnFr8orYCD81UD6hVqNl3nzSKnVSvSGn1R75AQEYPkrlQKNrdq1t61I8VsCVosjvsL2K8eHSIrCy/NigZQoqFTRhHSTZzdpRpLlwLE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704190109; c=relaxed/simple; bh=AdAN0Kak2KPI6da1a5K9HUe1O3dGF8h/F25JH17CnEA=; h=DKIM-Signature:Date:Message-Id:Mime-Version:From:To:Subject; b=XzhvEnurlXB920xYMbio1xUzSUMrvXyW02tLvX8jSmFf+D+dMhkjPuvbwmttbOBvBfcmoFQpN4JCYbjZG4uIu+fGOjdqHjCx5h89mW9ygu/oaBXycxsHnMz5RssnKfhGs+0we/tdKzdYJVcRFn33yqagmaBLUUF3tARV8KORtno= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1704190102; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=AdAN0Kak2KPI6da1a5K9HUe1O3dGF8h/F25JH17CnEA=; b=ikT/1MWozzzr1coqdUpmovurGNCzN0Z4ndNutYFnFtnPNebEl1IQ5ox4y5+6cobcvVlc04 wgJesmBDXDk1do3HxurqH7+eAHPScxmHgE0drYT2ZQsW80puZsovbQDD2TaPRmz+IgCMzj 5T4pvPFWxm6v0UWA733rAEweKzYJSF33WTAUjP/d0eiBpt4bIQY4dUrqYjDUcVdNZJh0Sw EVW5X23uX5vaN7Nor5w/9Nh1Ry/LzyNbxsZbAg2YAEObo8BxRC3qquqNxHv/oy7dW+745+ yPBs7u69HFOH57xOIKuPHve2frpmmuYXoTrckjNyZWb9J6BdB9ygW2EhrroSKQ== Date: Tue, 2 Jan 2024 18:08:19 +0800 Message-Id: Mime-Version: 1.0 References: <20231225103548.1615-2-zhujunxian@oss.cipunited.com> <20231225103548.1615-4-zhujunxian@oss.cipunited.com> <61ecc506-3796-49e1-a4f3-7a39807a1fc3@linaro.org> Received: from [192.168.8.110] ([171.15.158.108]) by smtp.feishu.cn with ESMTPS; Tue, 02 Jan 2024 18:08:21 +0800 In-Reply-To: X-Lms-Return-Path: From: "Junxian Zhu" User-Agent: Mozilla Thunderbird Content-Type: text/plain; charset=UTF-8 X-Original-From: Junxian Zhu To: "Xi Ruoyao" Cc: , Subject: Re: [PATCH 2/2] MIPS: Hard-float rounding instructions support Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00,DKIM_INVALID,DKIM_SIGNED,KAM_DMARC_STATUS,MSGID_FROM_MTA_HEADER,NO_DNS_FOR_FROM,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: =E5=9C=A8 2023/12/27 6:50, Xi Ruoyao =E5=86=99=E9=81=93: > On Wed, 2023-12-27 at 05:50 +0800, Xi Ruoyao wrote: >> On Tue, 2023-12-26 at 17:12 -0300, Adhemerval Zanella Netto wrote: >>> Also, I see no point in implementing this optimizations with assembly w= here >>> a C implementation would be way simpler and generate similar code. Simi= lar >>> to what I did for powerpc with sysdeps/powerpc/fpu/round_to_integer.h, = I >>> implemented a similar approach for MIPS [1].=C2=A0 The resulting code s= hould be >>> similar to the assembly implementation, taking in consideration the cor= rect >>> fix to save/restore floating-point exceptions. I did see no math regres= sion >>> on cfarm23 with a glibc built with -mabi=3D64 -mips64r2. >> Is there a micro-benchmark result on the cfarm machine?=C2=A0 AFAIK the = FCSR >> setting instruction may be much more slower than normal instructions, so >> I'm not sure if this is really a win. > Add Jiaxun who knows MIPS much better than me. After disscussion with Jiaxun, we guess that the consuming of switching=20 mode in FCSR is the cause of FPU implements slower than generic=20 implements. If we don't change or switching mode in FCSR, the FPU=20 implements will be faster than generic implements. Tested on Imagination=20 Ci40 (MIPS interAptiv (multi) V2.0=C2=A0 FPU V0.0)and loogson 3A2000. So it's enough to use generic C implements for rounding on MIPS.......