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Tue, 30 Apr 2024 18:13:46 +0000 (GMT) Message-ID: Date: Tue, 30 Apr 2024 13:13:45 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] powerpc: Fix __fesetround_inline_nocheck on POWER9+ (BZ 31682) To: Adhemerval Zanella , libc-alpha@sourceware.org Cc: Manjunath S Matti , Peter Bergner References: <20240430124011.12408-1-adhemerval.zanella@linaro.org> Content-Language: en-US From: Paul E Murphy In-Reply-To: <20240430124011.12408-1-adhemerval.zanella@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: H2AnW8-iv-jkMsii47yZ4agmswcZ98_r X-Proofpoint-ORIG-GUID: H2AnW8-iv-jkMsii47yZ4agmswcZ98_r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-30_11,2024-04-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 clxscore=1011 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=599 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2404010000 definitions=main-2404300131 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 4/30/24 7:40 AM, Adhemerval Zanella wrote: > The e68b1151f7460d5fa88c3a567c13f66052da79a7 commit changed the > __fesetround_inline_nocheck implementation to use mffscrni > (through __fe_mffscrn) instead of mtfsfi. For generic powerpc > ceil/floor/trunc, the function is supposed to not change the > Floating-Point Inexact Exception Enable bit, however mffscrni > clear bits 56:63 (VE, OE, UE, ZE, XE, NI, RN), different than mtfsfi. I don't think that explanation is correct. mffscrni should not alter the exception enable bits. It copies them into FRT, but does not clear them. From ISA 3.1 description of mffscrni: The contents of the control bits in the FPSCR, that is, bits 29:31 (DRN) and bits 56:63 (VE, OE, UE, ZE, XE, NI, RN), are placed into the corresponding bits in register FRT. All other bits in register FRT are set to 0. The contents of bits 62:63 of the FPSCR (RN) are set to the value of RM.