From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by sourceware.org (Postfix) with ESMTPS id 3B2E73858D33 for ; Thu, 23 May 2024 13:09:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3B2E73858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3B2E73858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::636 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716469759; cv=none; b=dxSaS+RcWutNomLZmX807BlLazMxTbV0zHXR5pgUEydwQACNy6/GZ0kF4PbSEeCy4ciFv2PU2W2FVre8U9uHGAfVaxKl5cmnNfZS0HjAdk1QDmw2BSAylFwHkUdEtm5+EGlePRVc+H5yKTU942F2PzcCOQd9uOWI97uxbZILojg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716469759; c=relaxed/simple; bh=LCx5g7FJxfgM8swNgWmaxJBehguP9CnuzQ0tP/uJqMg=; h=DKIM-Signature:Message-ID:Date:MIME-Version:Subject:To:From; b=d3d5nJdHsAvhQdM/exiyzEaWRWni9sVeaXb559+hc/sVBuTBzmGD8p+dp1irOH+kjQ4kro1dhrI9mDczKNeAlJG71Gd05d1QWxP+l/VW1PmrsX6lRLFh4uwwcnaSEoqDSo7Xq/IwdsWNMMhqy4lMNufIr4T8u0RiKfmlPKmL7oo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1f33d84eaefso5767675ad.3 for ; Thu, 23 May 2024 06:09:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716469754; x=1717074554; darn=sourceware.org; h=content-transfer-encoding:in-reply-to:organization:from :content-language:references:cc:to:subject:user-agent:mime-version :date:message-id:from:to:cc:subject:date:message-id:reply-to; bh=5RdHSmw5ngFrF5GVKoX+9pi3daXcpSAD/08J3LcYebI=; b=OvWaXtLwdeu35ktHUEJd5rryyt5f83iDtSCIIrhd8sX444fiTValS9ENPNlDqI/gw6 kNXYHg6HsRIfaZTJP/8lAaOVRHfZA3DRIOqNuC2hvlMyXwkOvVVf2r3qXL917zg0njET iyzZR/NW5aLGX9crmubEgcCWEYlXxMC1P50gOABALleeSNY/joYuJn583Okfb4E8jKlh z/iqHpD7yGcvCtWMoFjEvznLwWpr//mjfa1KyvMpbWHI2NBL++rasmXWPud3z8QlmPtq Jczc8pzuue4+g+8xkxWWP5iQxSZqGsPb+eIcNDKWkDgvzwI3oap0loFSKPbaKcHN7vRk ozxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716469754; x=1717074554; h=content-transfer-encoding:in-reply-to:organization:from :content-language:references:cc:to:subject:user-agent:mime-version :date:message-id:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=5RdHSmw5ngFrF5GVKoX+9pi3daXcpSAD/08J3LcYebI=; b=urAPDp4SDIpwi1WmLsv63DCppYdVwSZNYf1wV5wDE5NvSDYTWP/VT5Ux8qoQ3WOCax 7EP5Ke8X/X8ejFml3dmrrUkAHWsB/2sUZXw/CaqxD11ynfAjJzrhJVGVjgwKGSgPy34Q uiJM4KOa5FW68XGZk7JVUHqxaviPl2eZh1FcSHKYDN/xBitD9NSAL+XdqHbB3gZsAbva rVG++exkNHY3r14vNRph3EZor+TNXX2l7vu795DWs5Lc3JNFiN9MosNA9BTEihFb2K6H 8JsAf6bInXBvlND7o6uxmOksTtRPofsEdOlgVe8vNdsFe0CJG0dShHDELp7cOI+CL/MB uw+g== X-Forwarded-Encrypted: i=1; AJvYcCXxYEyGLpmCWZJShkTvsgnLrNrgel+SlizUhQZ0mF9UMre7suQqOG46I42Q+n6zkm/C1Bom1l3rOjWVJK7QRPVOrItJZH0GpS3r X-Gm-Message-State: AOJu0Yw3XcVa+V3GvAf1sUPeBNt0hLDHsHto2hcrvGfvXBeqRNrm8IwH BKdoX07VG+NJwmwZfybd3E0l2oqzgmEBB3FUSBY5k+4ifzhV/qK6PTyltsRPgQMuZ8/vsTjueyI n X-Google-Smtp-Source: AGHT+IFSyIUiqbLcWCt/TRWCXBvtIrV9yNfbg4oVfvhN3h4r9MgHfPVKur/8ll6f/8qEQqOGs9RBpw== X-Received: by 2002:a17:902:e88a:b0:1f3:4efa:6615 with SMTP id d9443c01a7336-1f34efa67c7mr6325585ad.27.1716469753945; Thu, 23 May 2024 06:09:13 -0700 (PDT) Received: from ?IPV6:2804:1b3:a7c3:7718:5dd8:d5e8:7ff2:a12a? ([2804:1b3:a7c3:7718:5dd8:d5e8:7ff2:a12a]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f2fe8280a2sm73384465ad.7.2024.05.23.06.09.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 May 2024 06:09:13 -0700 (PDT) Message-ID: Date: Thu, 23 May 2024 10:09:10 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] LoongArch: Use "$fcsr0" instead of "$r0" in _FPU_{GET,SET}CW To: Xi Ruoyao , libc-alpha@sourceware.org Cc: caiyinyu@loongson.cn, WANG Xuerui , luweining@loongson.cn References: <20240429073111.14572-2-xry111@xry111.site> Content-Language: en-US From: Adhemerval Zanella Netto Organization: Linaro In-Reply-To: <20240429073111.14572-2-xry111@xry111.site> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 29/04/24 04:31, Xi Ruoyao wrote: > Clang inline-asm parser does not allow using "$r0" in > movfcsr2gr/movgr2fcsr, so everything using _FPU_{GET,SET}CW is now > failing to build with Clang on LoongArch. As we now requires Binutils >> = 2.41 which supports using "$fcsr0" here, use it instead of "$r0" to > fix the issue. > > Link: https://github.com/loongson-community/discussions/issues/53#issuecomment-2081507390 > Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4142b2368353 > Signed-off-by: Xi Ruoyao LGTM, thanks. It is safe to use with old gcc and binutils or the new constraint required a specific gcc version? > --- > > People in the Cc list will receive this twice because I've mistyped the > address of libc-alpha first time. Sorry. Stupid I :(. > > sysdeps/loongarch/fpu_control.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/sysdeps/loongarch/fpu_control.h b/sysdeps/loongarch/fpu_control.h > index 54add4e01c..3cdf2417d9 100644 > --- a/sysdeps/loongarch/fpu_control.h > +++ b/sysdeps/loongarch/fpu_control.h > @@ -91,8 +91,8 @@ typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__))); > /* Macros for accessing the hardware control word. */ > extern fpu_control_t __loongarch_fpu_getcw (void) __THROW; > extern void __loongarch_fpu_setcw (fpu_control_t) __THROW; > -#define _FPU_GETCW(cw) __asm__ volatile ("movfcsr2gr %0,$r0" : "=r"(cw)) > -#define _FPU_SETCW(cw) __asm__ volatile ("movgr2fcsr $r0,%0" : : "r"(cw)) > +#define _FPU_GETCW(cw) __asm__ volatile ("movfcsr2gr %0,$fcsr0" : "=r"(cw)) > +#define _FPU_SETCW(cw) __asm__ volatile ("movgr2fcsr $fcsr0,%0" : : "r"(cw)) > > /* Default control word set at startup. */ > extern fpu_control_t __fpu_control;