[PATCH] powerpc: Use aligned stores in memset

[PATCH] powerpc: Use aligned stores in memset

[Rajalakshmi Srinivasaraghavan]

The powerpc hardware does not allow unaligned accesses on non cacheable
memory.  This patch avoids misaligned stores for sizes less than 8 in
memset to avoid such cases.  Tested on powerpc64 and powerpc64le.

2017-08-17  Rajalakshmi Srinivasaraghavan  <raji@linux.vnet.ibm.com>

	* sysdeps/powerpc/powerpc64/power8/memset.S: Store byte by byte
	for unaligned inputs if size is less than 8.
---
 sysdeps/powerpc/powerpc64/power8/memset.S | 68 ++++++++++++++++++++++++++++++-
 1 file changed, 66 insertions(+), 2 deletions(-)

diff --git a/sysdeps/powerpc/powerpc64/power8/memset.S b/sysdeps/powerpc/powerpc64/power8/memset.S
index 7ad3bb1b00..504bab0841 100644
--- a/sysdeps/powerpc/powerpc64/power8/memset.S
+++ b/sysdeps/powerpc/powerpc64/power8/memset.S
@@ -377,7 +377,8 @@ L(write_LT_32):
 	subf	r5,r0,r5
 
 2:	bf	30,1f
-	sth	r4,0(r10)
+	stb	r4,0(r10)
+	stb	r4,1(r10)
 	addi	r10,r10,2
 
 1:	bf	31,L(end_4bytes_alignment)
@@ -437,11 +438,74 @@ L(tail5):
 	/* Handles copies of 0~8 bytes.  */
 	.align	4
 L(write_LE_8):
-	bne	cr6,L(tail4)
+	/* Use stb instead of sth which is safe for
+	   both aligned and unaligned inputs.  */
+	bne	cr6,L(LE7_tail4)
+	/* If input is word aligned, use stw, Else use stb.  */
+	andi.	r0,r10,3
+	bne	L(8_unalign)
 
 	stw	r4,0(r10)
 	stw	r4,4(r10)
 	blr
+
+	/* Unaligned input and size is 8.  */
+	.align	4
+L(8_unalign):
+	andi.	r0,r10,1
+	beq	L(8_hwalign)
+	stb	r4,0(r10)
+	sth	r4,1(r10)
+	sth	r4,3(r10)
+	sth	r4,5(r10)
+	stb	r4,7(r10)
+	blr
+
+	/* Halfword aligned input and size is 8.  */
+	.align	4
+L(8_hwalign):
+	sth	r4,0(r10)
+	sth	r4,2(r10)
+	sth	r4,4(r10)
+	sth	r4,6(r10)
+	blr
+
+	.align	4
+	/* Copies 4~7 bytes.  */
+L(LE7_tail4):
+	bf	29,L(LE7_tail2)
+	stb	r4,0(r10)
+	stb	r4,1(r10)
+	stb	r4,2(r10)
+	stb	r4,3(r10)
+	bf	30,L(LE7_tail5)
+	stb	r4,4(r10)
+	stb	r4,5(r10)
+	bflr	31
+	stb	r4,6(r10)
+	blr
+
+	.align	4
+	/* Copies 2~3 bytes.  */
+L(LE7_tail2):
+	bf	30,1f
+	stb	r4,0(r10)
+	stb	r4,1(r10)
+	bflr	31
+	stb	r4,2(r10)
+	blr
+
+	.align	4
+L(LE7_tail5):
+	bflr	31
+	stb	r4,4(r10)
+	blr
+
+	.align	4
+1: 	bflr	31
+	stb	r4,0(r10)
+	blr
+
 END_GEN_TB (MEMSET,TB_TOCLESS)
 libc_hidden_builtin_def (memset)
 
-- 
2.11.0

Re: [PATCH] powerpc: Use aligned stores in memset

[Florian Weimer]

On 08/18/2017 07:11 AM, Rajalakshmi Srinivasaraghavan wrote:
> 	* sysdeps/powerpc/powerpc64/power8/memset.S: Store byte by byte
> 	for unaligned inputs if size is less than 8.

This makes me rather nervous.  powerpc64le was supposed to have
reasonable efficient unaligned loads and stores.  GCC happily generates
them, too.

Thanks,
Florian

Re: [PATCH] powerpc: Use aligned stores in memset

[Rajalakshmi Srinivasaraghavan]

On 08/18/2017 11:51 AM, Florian Weimer wrote:
> On 08/18/2017 07:11 AM, Rajalakshmi Srinivasaraghavan wrote:
>> 	* sysdeps/powerpc/powerpc64/power8/memset.S: Store byte by byte
>> 	for unaligned inputs if size is less than 8.
> 
> This makes me rather nervous.  powerpc64le was supposed to have
> reasonable efficient unaligned loads and stores.  GCC happily generates
> them, too.

This is meant ONLY for caching inhibited accesses.  Caching Inhibited 
accesses are required to be Guarded and properly aligned.

> 
> Thanks,
> Florian
> 
> 

-- 
Thanks
Rajalakshmi S

Re: [PATCH] powerpc: Use aligned stores in memset

[Florian Weimer]

On 08/18/2017 08:51 AM, Rajalakshmi Srinivasaraghavan wrote:
> 
> 
> On 08/18/2017 11:51 AM, Florian Weimer wrote:
>> On 08/18/2017 07:11 AM, Rajalakshmi Srinivasaraghavan wrote:
>>>     * sysdeps/powerpc/powerpc64/power8/memset.S: Store byte by byte
>>>     for unaligned inputs if size is less than 8.
>>
>> This makes me rather nervous.  powerpc64le was supposed to have
>> reasonable efficient unaligned loads and stores.  GCC happily generates
>> them, too.
> 
> This is meant ONLY for caching inhibited accesses.  Caching Inhibited
> accesses are required to be Guarded and properly aligned.

The intent is to support memset for such memory regions, right?  This
change is insufficient.  You have to fix GCC as well because it will
inline memset of unaligned pointers, like this:

typedef long __attribute__ ((aligned(1))) long_unaligned;

void
clear (long_unaligned *p)
{
  memset (p, 0, sizeof (*p));
}

clear:
	li 9,0
	std 9,0(3)
	blr

That's why I think your change is not useful in isolation.

Thanks,
Florian

Re: [PATCH] powerpc: Use aligned stores in memset

[Adhemerval Zanella]

On 18/08/2017 06:10, Florian Weimer wrote:
> On 08/18/2017 08:51 AM, Rajalakshmi Srinivasaraghavan wrote:
>>
>>
>> On 08/18/2017 11:51 AM, Florian Weimer wrote:
>>> On 08/18/2017 07:11 AM, Rajalakshmi Srinivasaraghavan wrote:
>>>>     * sysdeps/powerpc/powerpc64/power8/memset.S: Store byte by byte
>>>>     for unaligned inputs if size is less than 8.
>>>
>>> This makes me rather nervous.  powerpc64le was supposed to have
>>> reasonable efficient unaligned loads and stores.  GCC happily generates
>>> them, too.
>>
>> This is meant ONLY for caching inhibited accesses.  Caching Inhibited
>> accesses are required to be Guarded and properly aligned.
> 
> The intent is to support memset for such memory regions, right?  This
> change is insufficient.  You have to fix GCC as well because it will
> inline memset of unaligned pointers, like this:
> 
> typedef long __attribute__ ((aligned(1))) long_unaligned;
> 
> void
> clear (long_unaligned *p)
> {
>   memset (p, 0, sizeof (*p));
> }
> 
> clear:
> 	li 9,0
> 	std 9,0(3)
> 	blr
> 
> That's why I think your change is not useful in isolation.


POWER8 does have fast unaligned access memory and in fact unaligned access
could be used to provide a faster memcpy/memmove implementation (I created
one that I never sent upstream some time ago [1]). Unaligned accesses are
used extensively in some optimized str* implementation I created for POWER8. 
It also allows GCC to use unaligned access for builtin mem* operation without
issue on *most* of the cases.

The problem is memset/memcpy/memmove *specifically* are used in some userland
drivers for DMA (if I recall correctly for some XORG drivers) and for this
specific user cases using unaligned access, specially vector ones, will case
the kernel to trap on *every* unaligned instruction leading to abysmal
performance. That's why I pushed 87868c2418fb74357757e3b739ce5b76b17a8929
to fix this very issue for POWER7 memcpy.

We already discussed this same issue some time ago [2] to try overcome this
limitation. I think ideally the drivers that rely on aligned mem* operations
should we its own mem* operations (similar to how dpdk does [3]).

[1] https://github.com/zatrazz/glibc/commits/memopt-power8
[2] https://sourceware.org/ml/libc-alpha/2015-01/msg00130.html
[3] http://dpdk.org/browse/dpdk/tree/lib/librte_eal/common/include/arch/ppc_64/rte_memcpy.h

Re: [PATCH] powerpc: Use aligned stores in memset

[Florian Weimer]

On 08/18/2017 11:10 AM, Florian Weimer wrote:
> On 08/18/2017 08:51 AM, Rajalakshmi Srinivasaraghavan wrote:
>>
>>
>> On 08/18/2017 11:51 AM, Florian Weimer wrote:
>>> On 08/18/2017 07:11 AM, Rajalakshmi Srinivasaraghavan wrote:
>>>>     * sysdeps/powerpc/powerpc64/power8/memset.S: Store byte by byte
>>>>     for unaligned inputs if size is less than 8.
>>>
>>> This makes me rather nervous.  powerpc64le was supposed to have
>>> reasonable efficient unaligned loads and stores.  GCC happily generates
>>> them, too.
>>
>> This is meant ONLY for caching inhibited accesses.  Caching Inhibited
>> accesses are required to be Guarded and properly aligned.
> 
> The intent is to support memset for such memory regions, right?  This
> change is insufficient.  You have to fix GCC as well because it will
> inline memset of unaligned pointers, like this:

Here's a more complete example:


#include <assert.h>
#include <stdio.h>
#include <string.h>

typedef long __attribute__ ((aligned(1))) long_unaligned;

__attribute__ ((noinline, noclone, weak))
void
clear (long_unaligned *p)
{
  memset (p, 0, sizeof (*p));
}

struct data
{
  char misalign;
  long_unaligned data;
};

int
main (void)
{
  struct data *data = malloc (sizeof (*data));
  assert (data != NULL);
  long_unaligned *p = &data->data;
  printf ("pointer: %p\n", p);
  clear (p);
  return 0;
}

The clear function compiles to:

typedef long __attribute__ ((aligned(1))) long_unaligned;

void
clear (long_unaligned *p)
{
  memset (p, 0, sizeof (*p));
}

At run time, I get:

pointer: 0x10003c10011

This means that GCC introduced an unaligned store, no matter how memset
was implemented.

I could not find the manual which has the requirement that the mem*
functions do not use unaligned accesses.  Unless they are worded in a
very peculiar way, right now, the GCC/glibc combination does not comply
with a requirement that memset & Co. can be used for device memory access.

Furthermore, I find it very peculiar that over-reading device memory is
acceptable.  Some memory-mapped devices behave strangely if memory
locations are read out of order or multiple times, and the current glibc
implementation accesses locations which are outside the specified object
boundaries.

So I think the implementation constraint on the mem* functions is wrong.
 It leads to a slower implementation of the mem* function for most of
userspace which does not access device memory, and even for device
memory, it is probably not what you want.

Thanks,
Florian

Re: [PATCH] powerpc: Use aligned stores in memset

[Zack Weinberg]

On Tue, Sep 12, 2017 at 6:30 AM, Florian Weimer <fweimer@redhat.com> wrote:
>
> I could not find the manual which has the requirement that the mem*
> functions do not use unaligned accesses.  Unless they are worded in a
> very peculiar way, right now, the GCC/glibc combination does not comply
> with a requirement that memset & Co. can be used for device memory access.

mem* are required to behave as-if they access memory as an array of
unsigned char.  Therefore it is valid to give them arbitrarily
(un)aligned pointers.  The C abstract machine doesn't specifically
contemplate the possibility of a CPU that can do unaligned word reads
but maybe not to all memory addresses, but I would argue that if there
is such a CPU, then mem* are obliged to cope with it.

> ...the current glibc
> implementation accesses locations which are outside the specified object
> boundaries.

I think that's technically a defect.  Nothing in the C standard
licenses it to do that; we just get away with it because, on the
implementations to date, it's not observable (unless you go past the
end of a page, which you'll note there are a bunch of tests to ensure
we don't do).  If an over-read by a single byte is observable, then
mem* is not allowed to do that.

zw

Re: [PATCH] powerpc: Use aligned stores in memset

[Steven Munroe]

On Tue, 2017-09-12 at 08:18 -0400, Zack Weinberg wrote:
> On Tue, Sep 12, 2017 at 6:30 AM, Florian Weimer <fweimer@redhat.com> wrote:
> >
> > I could not find the manual which has the requirement that the mem*
> > functions do not use unaligned accesses.  Unless they are worded in a
> > very peculiar way, right now, the GCC/glibc combination does not comply
> > with a requirement that memset & Co. can be used for device memory access.
> 
> mem* are required to behave as-if they access memory as an array of
> unsigned char.  Therefore it is valid to give them arbitrarily
> (un)aligned pointers.  The C abstract machine doesn't specifically
> contemplate the possibility of a CPU that can do unaligned word reads
> but maybe not to all memory addresses, but I would argue that if there
> is such a CPU, then mem* are obliged to cope with it.
> 
> > ...the current glibc
> > implementation accesses locations which are outside the specified object
> > boundaries.
> 
> I think that's technically a defect.  Nothing in the C standard
> licenses it to do that; we just get away with it because, on the
> implementations to date, it's not observable (unless you go past the
> end of a page, which you'll note there are a bunch of tests to ensure
> we don't do).  If an over-read by a single byte is observable, then
> mem* is not allowed to do that.
> 
Also a bit of over reaction.

As long a the library routine does no cause a visible artifact (segfault
or alignment check) aligned access before or after the requested start
address and length is an optimization.

For example accessing the source at offset 3 and length 10 with an
aligned quadword load is Ok as long I clear the leading and trailing
bytes.

But attempting to store 7 bytes within a quadword by merging bytes in a
register and storing the whole quadword would violate single copy
atomicity and is not allowed.

> zw
> 

Re: [PATCH] powerpc: Use aligned stores in memset

[Joseph Myers]

On Tue, 12 Sep 2017, Zack Weinberg wrote:

> On Tue, Sep 12, 2017 at 6:30 AM, Florian Weimer <fweimer@redhat.com> wrote:
> >
> > I could not find the manual which has the requirement that the mem*
> > functions do not use unaligned accesses.  Unless they are worded in a
> > very peculiar way, right now, the GCC/glibc combination does not comply
> > with a requirement that memset & Co. can be used for device memory access.
> 
> mem* are required to behave as-if they access memory as an array of
> unsigned char.  Therefore it is valid to give them arbitrarily
> (un)aligned pointers.  The C abstract machine doesn't specifically
> contemplate the possibility of a CPU that can do unaligned word reads
> but maybe not to all memory addresses, but I would argue that if there
> is such a CPU, then mem* are obliged to cope with it.

Only if there is a way, within the standard, in which you might obtain a 
pointer to such memory.

It is explicitly undefined in ISO C to access "an object defined with a 
volatile-qualified type through use of an lvalue with 
non-volatile-qualified type" (C11 6.7.3#6).  Thus you can't use mem* 
functions on objects defined as volatile.  I think device memory with 
special access requirements should be considered to be defined as 
volatile.  (So any access from C code should use volatile-qualified 
lvalues.)

-- 
Joseph S. Myers
joseph@codesourcery.com

Re: [PATCH] powerpc: Use aligned stores in memset

[Zack Weinberg]

On Tue, Sep 12, 2017 at 10:37 AM, Joseph Myers <joseph@codesourcery.com> wrote:
> On Tue, 12 Sep 2017, Zack Weinberg wrote:
>>
>> mem* are required to behave as-if they access memory as an array of
>> unsigned char.  Therefore it is valid to give them arbitrarily
>> (un)aligned pointers.  The C abstract machine doesn't specifically
>> contemplate the possibility of a CPU that can do unaligned word reads
>> but maybe not to all memory addresses, but I would argue that if there
>> is such a CPU, then mem* are obliged to cope with it.
>
> Only if there is a way, within the standard, in which you might obtain a
> pointer to such memory.

Perhaps it is only a matter of QoI, but I would argue that if there is
_any_ way to obtain such a pointer, considering the entire operating
system, then mem* can and should cope with it.

> I think device memory with
> special access requirements should be considered to be defined as
> volatile.  (So any access from C code should use volatile-qualified
> lvalues.)

I know you know that's violently disputed.

zw

Re: [PATCH] powerpc: Use aligned stores in memset

[Florian Weimer]

On 09/12/2017 02:18 PM, Zack Weinberg wrote:
> On Tue, Sep 12, 2017 at 6:30 AM, Florian Weimer <fweimer@redhat.com> wrote:
>>
>> I could not find the manual which has the requirement that the mem*
>> functions do not use unaligned accesses.  Unless they are worded in a
>> very peculiar way, right now, the GCC/glibc combination does not comply
>> with a requirement that memset & Co. can be used for device memory access.
> 
> mem* are required to behave as-if they access memory as an array of
> unsigned char.  Therefore it is valid to give them arbitrarily
> (un)aligned pointers.  The C abstract machine doesn't specifically
> contemplate the possibility of a CPU that can do unaligned word reads
> but maybe not to all memory addresses, but I would argue that if there
> is such a CPU, then mem* are obliged to cope with it.

I disagree.  On most architectures, including x86-64, you can tell, with
certain hardware devices, that our mem* functions do not perform
byte-wise read or write access.  On many architectures, just a hardware
watchpoint installed using ptrace (a supported API) is sufficient.  But
this theoretical possibility does not mean that we cannot or should not
optimize the mem* functions.

If you need specific memory access patterns, you need to use inline
assembly.  In many cases, volatile loads and stores are sufficient, too.

>> ...the current glibc
>> implementation accesses locations which are outside the specified object
>> boundaries.
> 
> I think that's technically a defect.  Nothing in the C standard
> licenses it to do that;

It's permitted under the as-if rule.

Florian

Re: [PATCH] powerpc: Use aligned stores in memset

[Steven Munroe]

On Tue, 2017-09-12 at 12:30 +0200, Florian Weimer wrote:
> On 08/18/2017 11:10 AM, Florian Weimer wrote:
> > On 08/18/2017 08:51 AM, Rajalakshmi Srinivasaraghavan wrote:
> >>
> >>
> >> On 08/18/2017 11:51 AM, Florian Weimer wrote:
> >>> On 08/18/2017 07:11 AM, Rajalakshmi Srinivasaraghavan wrote:
> >>>>     * sysdeps/powerpc/powerpc64/power8/memset.S: Store byte by byte
> >>>>     for unaligned inputs if size is less than 8.
> >>>
> >>> This makes me rather nervous.  powerpc64le was supposed to have
> >>> reasonable efficient unaligned loads and stores.  GCC happily generates
> >>> them, too.
> >>
> >> This is meant ONLY for caching inhibited accesses.  Caching Inhibited
> >> accesses are required to be Guarded and properly aligned.
> > 
> > The intent is to support memset for such memory regions, right?  This
> > change is insufficient.  You have to fix GCC as well because it will
> > inline memset of unaligned pointers, like this:
> 
> Here's a more complete example:
> 

..snip

> 
> This means that GCC introduced an unaligned store, no matter how memset
> was implemented.
> 
C will do what ever the programmer wants. We can not stop that. 

And in user mode and cache coherent memory this is not a problem as
Adhemerval explained.

So we are not going to degrade the performance of general applications
for a tiny subset of specialized device drivers. Those guy have to know
what they are doing.

But in the library (like libc) that might be called from a user mode
device driver (Xorg for example) and access Cache inhibited memory the
memcpy implementation has to check alignment and size and using the
correct instructions for each case.

That is what we are doing here. 


> I could not find the manual which has the requirement that the mem*
> functions do not use unaligned accesses.  Unless they are worded in a
> very peculiar way, right now, the GCC/glibc combination does not comply
> with a requirement that memset & Co. can be used for device memory access.
> 
> Furthermore, I find it very peculiar that over-reading device memory is
> acceptable.  Some memory-mapped devices behave strangely if memory
> locations are read out of order or multiple times, and the current glibc
> implementation accesses locations which are outside the specified object
> boundaries.
> 
Yes device driver writers have to know what they are doing.

> So I think the implementation constraint on the mem* functions is wrong.
>  It leads to a slower implementation of the mem* function for most of
> userspace which does not access device memory, and even for device
> memory, it is probably not what you want.
> 
We are just trying to make the mem* safe (not segfault or alignment
check) if used correctly. 

The definition of correctly is a bit fluid. I personally disagree with
the Xorg folks but so far they have refused to bend...


> Thanks,
> Florian
> 

Re: [PATCH] powerpc: Use aligned stores in memset

[Florian Weimer]

* Steven Munroe:

>> This means that GCC introduced an unaligned store, no matter how memset
>> was implemented.
>> 
> C will do what ever the programmer wants. We can not stop that.

That's not true.  If some specification says that for POWER, mem* must
behave in a certain way, and the GCC/glibc combiniation does not do
that, that's a bug on POWER.

The programmer only sees the entire toolchain, and it is our job to
make the whole thing compliant with applicable specifications, even if
this means coordinating among different projects.

> And in user mode and cache coherent memory this is not a problem as
> Adhemerval explained.

Obviously not, otherwise we wouldn't be changing glibc.

> So we are not going to degrade the performance of general applications
> for a tiny subset of specialized device drivers. Those guy have to know
> what they are doing.
>
> But in the library (like libc) that might be called from a user mode
> device driver (Xorg for example) and access Cache inhibited memory the
> memcpy implementation has to check alignment and size and using the
> correct instructions for each case.
>
> That is what we are doing here.

Sorry, but you are contradicting yourself.  I very much doubt the
Xorg-compatible memcmp is an improvement across the board.

Re: [PATCH] powerpc: Use aligned stores in memset

[Steven Munroe]

On Tue, 2017-09-12 at 16:08 +0200, Florian Weimer wrote:
> * Steven Munroe:
> 
> >> This means that GCC introduced an unaligned store, no matter how memset
> >> was implemented.
> >> 
> > C will do what ever the programmer wants. We can not stop that.
> 
> That's not true.  If some specification says that for POWER, mem* must
> behave in a certain way, and the GCC/glibc combiniation does not do
> that, that's a bug on POWER.
> 
What is the bug that you think we are not fixing?

> The programmer only sees the entire toolchain, and it is our job to
> make the whole thing compliant with applicable specifications, even if
> this means coordinating among different projects.
> 
> > And in user mode and cache coherent memory this is not a problem as
> > Adhemerval explained.
> 
> Obviously not, otherwise we wouldn't be changing glibc.
> 
I was arguing against forcing GCC and compilers in general being forced
to be aware of Cache Inhibited memory. Programmers do.

What are you arguing? 

> > So we are not going to degrade the performance of general applications
> > for a tiny subset of specialized device drivers. Those guy have to know
> > what they are doing.
> >
> > But in the library (like libc) that might be called from a user mode
> > device driver (Xorg for example) and access Cache inhibited memory the
> > memcpy implementation has to check alignment and size and using the
> > correct instructions for each case.
> >
> > That is what we are doing here.
> 
> Sorry, but you are contradicting yourself.  I very much doubt the
> Xorg-compatible memcmp is an improvement across the board.
> 

Re: [PATCH] powerpc: Use aligned stores in memset

[Florian Weimer]

On 09/12/2017 04:16 PM, Steven Munroe wrote:
> On Tue, 2017-09-12 at 16:08 +0200, Florian Weimer wrote:
>> * Steven Munroe:
>>
>>>> This means that GCC introduced an unaligned store, no matter how memset
>>>> was implemented.
>>>>
>>> C will do what ever the programmer wants. We can not stop that.
>>
>> That's not true.  If some specification says that for POWER, mem* must
>> behave in a certain way, and the GCC/glibc combiniation does not do
>> that, that's a bug on POWER.
>>
> What is the bug that you think we are not fixing?

memset, as called by the C programmer, still uses unaligned stores.

>> The programmer only sees the entire toolchain, and it is our job to
>> make the whole thing compliant with applicable specifications, even if
>> this means coordinating among different projects.
>>
>>> And in user mode and cache coherent memory this is not a problem as
>>> Adhemerval explained.
>>
>> Obviously not, otherwise we wouldn't be changing glibc.
>>
> I was arguing against forcing GCC and compilers in general being forced
> to be aware of Cache Inhibited memory. Programmers do.

Exactly.  In order to give programmers this choice, you need functions
like device_memset, which are not subject to compiler or library
optimizations which are not valid for device memory.

> What are you arguing? 

If you want a memset which is compatible with device memory, you need to
fix GCC *and* glibc.  Just patching glibc is not enough because GCC
optimizes memset in ways that are incompatible with your apparent goal..

Thanks,
Florian

Re: [PATCH] powerpc: Use aligned stores in memset

[Steven Munroe]

On Tue, 2017-09-12 at 19:04 +0200, Florian Weimer wrote:
> On 09/12/2017 04:16 PM, Steven Munroe wrote:
> > On Tue, 2017-09-12 at 16:08 +0200, Florian Weimer wrote:
> >> * Steven Munroe:
> >>
> >>>> This means that GCC introduced an unaligned store, no matter how memset
> >>>> was implemented.
> >>>>
> >>> C will do what ever the programmer wants. We can not stop that.
> >>
> >> That's not true.  If some specification says that for POWER, mem* must
> >> behave in a certain way, and the GCC/glibc combiniation does not do
> >> that, that's a bug on POWER.
> >>
> > What is the bug that you think we are not fixing?
> 
> memset, as called by the C programmer, still uses unaligned stores.
> 

Are you sure? Which one?

find ./ -name 'memset*' | grep powerpc
./sysdeps/powerpc/powerpc32/power7/memset.S
./sysdeps/powerpc/powerpc32/memset.S
./sysdeps/powerpc/powerpc32/476/memset.S
./sysdeps/powerpc/powerpc32/405/memset.S
./sysdeps/powerpc/powerpc32/power6/memset.S
./sysdeps/powerpc/powerpc32/power4/memset.S
./sysdeps/powerpc/powerpc32/power4/multiarch/memset-ppc32.S
./sysdeps/powerpc/powerpc32/power4/multiarch/memset-power6.S
./sysdeps/powerpc/powerpc32/power4/multiarch/memset.c
./sysdeps/powerpc/powerpc32/power4/multiarch/memset-power7.S
./sysdeps/powerpc/powerpc64/power8/memset.S
./sysdeps/powerpc/powerpc64/power7/memset.S
./sysdeps/powerpc/powerpc64/memset.S
./sysdeps/powerpc/powerpc64/multiarch/memset-power8.S
./sysdeps/powerpc/powerpc64/multiarch/memset-power4.S
./sysdeps/powerpc/powerpc64/multiarch/memset-power6.S
./sysdeps/powerpc/powerpc64/multiarch/memset.c
./sysdeps/powerpc/powerpc64/multiarch/memset-ppc64.S
./sysdeps/powerpc/powerpc64/multiarch/memset-power7.S
./sysdeps/powerpc/powerpc64/power6/memset.S
./sysdeps/powerpc/powerpc64/power4/memset.S

> >> The programmer only sees the entire toolchain, and it is our job to
> >> make the whole thing compliant with applicable specifications, even if
> >> this means coordinating among different projects.
> >>
> >>> And in user mode and cache coherent memory this is not a problem as
> >>> Adhemerval explained.
> >>
> >> Obviously not, otherwise we wouldn't be changing glibc.
> >>
> > I was arguing against forcing GCC and compilers in general being forced
> > to be aware of Cache Inhibited memory. Programmers do.
> 
> Exactly.  In order to give programmers this choice, you need functions
> like device_memset, which are not subject to compiler or library
> optimizations which are not valid for device memory.
> 
Which project is going to host device_memset?

Are you suggesting that GLIBC should?

> > What are you arguing? 
> 
> If you want a memset which is compatible with device memory, you need to
> fix GCC *and* glibc.  Just patching glibc is not enough because GCC
> optimizes memset in ways that are incompatible with your apparent goal..
> 
I still don't see how GCC changes are required for this.

You need to specific here.

We are not going to version every loop that might contain stores based
on speculation that someone who does not know what they are doing might
access Cache Inhibited storage.

Not going to happen.

> Thanks,
> Florian
> 

Re: [PATCH] powerpc: Use aligned stores in memset

[Florian Weimer]

On 09/12/2017 09:21 PM, Steven Munroe wrote:
> On Tue, 2017-09-12 at 19:04 +0200, Florian Weimer wrote:
>> On 09/12/2017 04:16 PM, Steven Munroe wrote:
>>> On Tue, 2017-09-12 at 16:08 +0200, Florian Weimer wrote:
>>>> * Steven Munroe:
>>>>
>>>>>> This means that GCC introduced an unaligned store, no matter how memset
>>>>>> was implemented.
>>>>>>
>>>>> C will do what ever the programmer wants. We can not stop that.
>>>>
>>>> That's not true.  If some specification says that for POWER, mem* must
>>>> behave in a certain way, and the GCC/glibc combiniation does not do
>>>> that, that's a bug on POWER.
>>>>
>>> What is the bug that you think we are not fixing?
>>
>> memset, as called by the C programmer, still uses unaligned stores.

Please look at my example and its disassembly.

> We are not going to version every loop that might contain stores based
> on speculation that someone who does not know what they are doing might
> access Cache Inhibited storage.

You need to remove optimizations from GCC which expand memset calls
using other instructions if those expansions do not compensate for the
possibility of unaligned stores.

Thanks,
Florian

Re: [PATCH] powerpc: Use aligned stores in memset

[Steven Munroe]

On Tue, 2017-09-12 at 21:45 +0200, Florian Weimer wrote:
> On 09/12/2017 09:21 PM, Steven Munroe wrote:
> > On Tue, 2017-09-12 at 19:04 +0200, Florian Weimer wrote:
> >> On 09/12/2017 04:16 PM, Steven Munroe wrote:
> >>> On Tue, 2017-09-12 at 16:08 +0200, Florian Weimer wrote:
> >>>> * Steven Munroe:
> >>>>
> >>>>>> This means that GCC introduced an unaligned store, no matter how memset
> >>>>>> was implemented.
> >>>>>>
> >>>>> C will do what ever the programmer wants. We can not stop that.
> >>>>
> >>>> That's not true.  If some specification says that for POWER, mem* must
> >>>> behave in a certain way, and the GCC/glibc combiniation does not do
> >>>> that, that's a bug on POWER.
> >>>>
> >>> What is the bug that you think we are not fixing?
> >>
> >> memset, as called by the C programmer, still uses unaligned stores.
> 
> Please look at my example and its disassembly.
> 
> > We are not going to version every loop that might contain stores based
> > on speculation that someone who does not know what they are doing might
> > access Cache Inhibited storage.
> 
> You need to remove optimizations from GCC which expand memset calls
> using other instructions if those expansions do not compensate for the
> possibility of unaligned stores.
> 
No, the programmer should use -fno-builtin-memset if that programmer
knows he is accessing cache inhibited space.

To be clear this is not new, cache coherent and cache inhibited storage
have been in the PowerISA from the beginning.

So why all the fuss now?

Re: [PATCH] powerpc: Use aligned stores in memset

[Tulio Magno Quites Machado Filho]

Florian Weimer <fweimer@redhat.com> writes:

> On 08/18/2017 11:10 AM, Florian Weimer wrote:
>> On 08/18/2017 08:51 AM, Rajalakshmi Srinivasaraghavan wrote:
>>>
>>>
>>> On 08/18/2017 11:51 AM, Florian Weimer wrote:
>>>> On 08/18/2017 07:11 AM, Rajalakshmi Srinivasaraghavan wrote:
>>>>>     * sysdeps/powerpc/powerpc64/power8/memset.S: Store byte by byte
>>>>>     for unaligned inputs if size is less than 8.
>>>>
>>>> This makes me rather nervous.  powerpc64le was supposed to have
>>>> reasonable efficient unaligned loads and stores.  GCC happily generates
>>>> them, too.
>>>
>>> This is meant ONLY for caching inhibited accesses.  Caching Inhibited
>>> accesses are required to be Guarded and properly aligned.
>> 
>> The intent is to support memset for such memory regions, right?  This
>> change is insufficient.  You have to fix GCC as well because it will
>> inline memset of unaligned pointers, like this:
>
> Here's a more complete example:
>
>
> #include <assert.h>
> #include <stdio.h>
> #include <string.h>
>
> typedef long __attribute__ ((aligned(1))) long_unaligned;
>
> __attribute__ ((noinline, noclone, weak))
> void
> clear (long_unaligned *p)
> {
>   memset (p, 0, sizeof (*p));
> }
>
> struct data
> {
>   char misalign;
>   long_unaligned data;
> };
>
> int
> main (void)
> {
>   struct data *data = malloc (sizeof (*data));
>   assert (data != NULL);
>   long_unaligned *p = &data->data;
>   printf ("pointer: %p\n", p);
>   clear (p);
>   return 0;
> }
>
> The clear function compiles to:
>
> typedef long __attribute__ ((aligned(1))) long_unaligned;
>
> void
> clear (long_unaligned *p)
> {
>   memset (p, 0, sizeof (*p));
> }
>
> At run time, I get:
>
> pointer: 0x10003c10011
>
> This means that GCC introduced an unaligned store, no matter how memset
> was implemented.

Which isn't necessarily a problem.
The performance penalty only appears when the memory access is referring
to an address which isn't at the instruction's natural boundary.

In this case, memset should use stb to avoid an alignment interrupt.

Notice that if the memory access is not at the natural boundary, an alignment
interrupt is generated and it won't generate an error.  The access will still
happen, but it will have a performance penalty.

> So I think the implementation constraint on the mem* functions is wrong.
>  It leads to a slower implementation of the mem* function for most of
> userspace which does not access device memory, and even for device
> memory, it is probably not what you want.

Makes sense.  But as there is nothing in the standard allowing or prohibiting
the usage of mem* functions to access caching-inhibited memory, I thought it
would make sense to provide functions that are as generic as possible.

IMHO, it's easier for programmers to use generic functions in most scenarios
and have access to specialized functions, e.g. a function for data already
aligned at 16 bytes.

-- 
Tulio Magno

Re: [PATCH] powerpc: Use aligned stores in memset

[Florian Weimer]

On 09/13/2017 03:12 PM, Tulio Magno Quites Machado Filho wrote:
>> So I think the implementation constraint on the mem* functions is wrong.
>>   It leads to a slower implementation of the mem* function for most of
>> userspace which does not access device memory, and even for device
>> memory, it is probably not what you want.
> Makes sense.  But as there is nothing in the standard allowing or prohibiting
> the usage of mem* functions to access caching-inhibited memory, I thought it
> would make sense to provide functions that are as generic as possible.

But I have shown that you aren't doing that because of the GCC 
optimization which inlines the memset call.

But I won't continue this conversation as I don't see it particularly 
useful to anyone.  In the end, you are the architecture maintainers, and 
you should do what you think is best.

Thanks,
Florian

Re: [PATCH] powerpc: Use aligned stores in memset

[Adhemerval Zanella]

[-- Attachment #1: Type: text/plain, Size: 2791 bytes --]



On 18/09/2017 10:54, Florian Weimer wrote:
> On 09/13/2017 03:12 PM, Tulio Magno Quites Machado Filho wrote:
>>> So I think the implementation constraint on the mem* functions is wrong.
>>>   It leads to a slower implementation of the mem* function for most of
>>> userspace which does not access device memory, and even for device
>>> memory, it is probably not what you want.
>> Makes sense.  But as there is nothing in the standard allowing or prohibiting
>> the usage of mem* functions to access caching-inhibited memory, I thought it
>> would make sense to provide functions that are as generic as possible.
> 
> But I have shown that you aren't doing that because of the GCC optimization which inlines the memset call.
> 
> But I won't continue this conversation as I don't see it particularly useful to anyone.  In the end, you are the architecture maintainers, and you should do what you think is best.
> 
> Thanks,
> Florian

I think one way to provide a slight better memcpy implementation for POWER8
and still be able to circumvent the non-aligned on non-cacheable memory
is to use tunables.

The branch azanella/memcpy-power8 [1] has a power8 memcpy optimization which
uses unaligned load and stores that I created some time ago but never actually
send upstream.  It shows better performance on both bench-memcpy and
bench-memcpy-random (about 10% on latter) and mixed results on bench-memcpy-large
(which it is mainly dominated by memory throughput and on the environment I am
using, a shared PowerKVM instance, the results does not seem to be reliable).

It could use some tunning, specially on some the range I used for unrolling
the load/stores and it also does not care for unaligned access on cross-page
boundary (which tend to be quite slow on current hardware, but also on
current page size of usual 64k also uncommon).

This first patch does not enable this option as a default for POWER8, it just
add on string tests as an option.  The second patch changes the selection to:

  1. If glibc is configure with tunables, set the new implementation as the
     default for ISA 2.07 (power8).

  2. Also if tunable is active, add the parameter glibc.tune.aligned_memopt
     to disable the new implementation selection.

So programs that rely on aligned loads can set:

GLIBC_TUNABLES=glibc.tune.aligned_memopt=1

And then the memcpy ifunc selection would pick the power7 one which uses
only aligned load and stores.

This is a RFC patch and if the idea sounds to powerpc arch mantainers I can
work on finishing the patch with more comments and send upstream.  I tried
to apply same unaligned idea for memset and memmove, but I could get any real
improvement in neither.

[1] https://sourceware.org/git/?p=glibc.git;a=shortlog;h=refs/heads/azanella/memcpy-power8

[-- Attachment #2: bench-memcpy-random.out --]
[-- Type: text/plain, Size: 769 bytes --]

{
 "timing_type": "hp_timing",
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[-- Attachment #3: bench-memcpy.out --]
[-- Type: text/plain, Size: 67126 bytes --]

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}

Re: [PATCH] powerpc: Use aligned stores in memset

[Rajalakshmi Srinivasaraghavan]

On 10/03/2017 11:59 PM, Adhemerval Zanella wrote:
> I think one way to provide a slight better memcpy implementation for POWER8
> and still be able to circumvent the non-aligned on non-cacheable memory
> is to use tunables.
> 
> The branch azanella/memcpy-power8 [1] has a power8 memcpy optimization which
> uses unaligned load and stores that I created some time ago but never actually
> send upstream.  It shows better performance on both bench-memcpy and
> bench-memcpy-random (about 10% on latter) and mixed results on bench-memcpy-large
> (which it is mainly dominated by memory throughput and on the environment I am
> using, a shared PowerKVM instance, the results does not seem to be reliable).
> 
> It could use some tunning, specially on some the range I used for unrolling
> the load/stores and it also does not care for unaligned access on cross-page
> boundary (which tend to be quite slow on current hardware, but also on
> current page size of usual 64k also uncommon).
> 
> This first patch does not enable this option as a default for POWER8, it just
> add on string tests as an option.  The second patch changes the selection to:
> 
>    1. If glibc is configure with tunables, set the new implementation as the
>       default for ISA 2.07 (power8).
> 
>    2. Also if tunable is active, add the parameter glibc.tune.aligned_memopt
>       to disable the new implementation selection.
> 
> So programs that rely on aligned loads can set:
> 
> GLIBC_TUNABLES=glibc.tune.aligned_memopt=1
> 
> And then the memcpy ifunc selection would pick the power7 one which uses
> only aligned load and stores.
> 
> This is a RFC patch and if the idea sounds to powerpc arch mantainers I can
> work on finishing the patch with more comments and send upstream.  I tried
> to apply same unaligned idea for memset and memmove, but I could get any real
> improvement in neither.
> 
> [1]https://sourceware.org/git/?p=glibc.git;a=shortlog;h=refs/heads/azanella/memcpy-power8

Thanks for sharing the patches. At this point we are also working on
memcpy for power8 with a different approach and we are planning
to post it soon. We can choose the better performing version and
use your tunables patch too.

-- 
Thanks
Rajalakshmi S

Re: [PATCH] powerpc: Use aligned stores in memset

[Tulio Magno Quites Machado Filho]

Adhemerval Zanella <adhemerval.zanella@linaro.org> writes:

> I think one way to provide a slight better memcpy implementation for POWER8
> and still be able to circumvent the non-aligned on non-cacheable memory
> is to use tunables.
>
> The branch azanella/memcpy-power8 [1] has a power8 memcpy optimization which
> uses unaligned load and stores that I created some time ago but never actually
> send upstream.  It shows better performance on both bench-memcpy and
> bench-memcpy-random (about 10% on latter) and mixed results on bench-memcpy-large
> (which it is mainly dominated by memory throughput and on the environment I am
> using, a shared PowerKVM instance, the results does not seem to be reliable).
>
> It could use some tunning, specially on some the range I used for unrolling
> the load/stores and it also does not care for unaligned access on cross-page
> boundary (which tend to be quite slow on current hardware, but also on
> current page size of usual 64k also uncommon).
>
> This first patch does not enable this option as a default for POWER8, it just
> add on string tests as an option.  The second patch changes the selection to:
>
>   1. If glibc is configure with tunables, set the new implementation as the
>      default for ISA 2.07 (power8).
>
>   2. Also if tunable is active, add the parameter glibc.tune.aligned_memopt
>      to disable the new implementation selection.

I think it would be safer if we don't change the default behavior.
IMHO, programs that want a performance improvement would have to set a
tunable.

In other words, the new implementation would be disabled by default.

> So programs that rely on aligned loads can set:
>
> GLIBC_TUNABLES=glibc.tune.aligned_memopt=1

I also think that we should not expose internal details of the implementation
to users, i.e. avoiding to use aligned/unaligned in the name of the function
and in the tunables.
I think that glibc.tune.cached_memopt=1 better exposes what is the optimal
use-case scenario of this implementation.

> This is a RFC patch and if the idea sounds to powerpc arch mantainers I can
> work on finishing the patch with more comments and send upstream.  I tried
> to apply same unaligned idea for memset and memmove, but I could get any real
> improvement in neither.

I like the idea.  Could you merge both patches and send it to libc-alpha,
please?

> [1] https://sourceware.org/git/?p=glibc.git;a=shortlog;h=refs/heads/azanella/memcpy-power8
> [ bench-memcpy-random.out: text/plain ]
> {
>  "timing_type": "hp_timing",
>  "functions": {
>   "memcpy": {
>    "bench-variant": "random",
>    "ifuncs": ["__memcpy_power8",

I also suggest give a more specific name, e.g. __memcpy_power8_cached.
That would make room for a POWER8 implementation what uses only naturally
aligned loads/stores.

Your implementation uses lxvd2x and stxvd2x, which should be avoided in a
cache-inhibited scenario, i.e. glibc.tune.aligned_memopt=0.

However, after changing the tunables' name to glibc.tune.cached_memopt, I think
these instructions could stay they're executed when glibc.tune.cached_memopt=1.

Thanks!!!

-- 
Tulio Magno

[PATCHv2] powerpc: POWER8 memcpy optimization for cached memory

[Tulio Magno Quites Machado Filho]

From: Adhemerval Zanella <azanella@linux.vnet.ibm.com>

I made the changes I requested, updated copyright entries, added a
manual entry and fixed a build issue on powerpc64.

--- 8< ---

On POWER8, unaligned memory accesses to cached memory has little impact
on performance as opposed to its ancestors.

It is disabled by default and will only be available when the tunable
glibc.tune.cached_memopt is set to 1.

                 __memcpy_power8_cached      __memcpy_power7
============================================================
    max-size=4096:     33325.70 ( 12.65%)        38153.00
    max-size=8192:     32878.20 ( 11.17%)        37012.30
   max-size=16384:     33782.20 ( 11.61%)        38219.20
   max-size=32768:     33296.20 ( 11.30%)        37538.30
   max-size=65536:     33765.60 ( 10.53%)        37738.40

2017-12-08  Adhemerval Zanella  <azanella@linux.vnet.ibm.com>
	    Tulio Magno Quites Machado Filho  <tuliom@linux.vnet.ibm.com>

	* manual/tunables.texi (Hardware Capability Tunables): Document
	glibc.tune.cached_memopt.
	* sysdeps/powerpc/cpu-features.c: New file.
	* sysdeps/powerpc/cpu-features.h: New file.
	* sysdeps/powerpc/dl-procinfo.c [!IS_IN(ldconfig)]: Add
	_dl_powerpc_cpu_features.
	* sysdeps/powerpc/dl-tunables.list: New file.
	* sysdeps/powerpc/ldsodefs.h: Include cpu-features.h.
	* sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h: .
	* sysdeps/powerpc/powerpc64/dl-machine.h (INIT_ARCH): Initialize
	use_aligned_memopt.
	* sysdeps/powerpc/powerpc64/multiarch/Makefile (sysdep_routines):
	Add memcpy-power8-cached.
	* sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c: Add
	__memcpy_power8_cached.
	* sysdeps/powerpc/powerpc64/multiarch/memcpy.c: Likewise.
	* sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S:
	New file.
---
 manual/tunables.texi                               |   7 +
 sysdeps/powerpc/cpu-features.c                     |  39 +++++
 sysdeps/powerpc/cpu-features.h                     |  28 ++++
 sysdeps/powerpc/dl-procinfo.c                      |  16 ++
 sysdeps/powerpc/dl-tunables.list                   |  28 ++++
 sysdeps/powerpc/ldsodefs.h                         |   1 +
 .../powerpc/powerpc32/power4/multiarch/init-arch.h |   2 +
 sysdeps/powerpc/powerpc64/dl-machine.h             |   4 +-
 sysdeps/powerpc/powerpc64/multiarch/Makefile       |   4 +-
 .../powerpc/powerpc64/multiarch/ifunc-impl-list.c  |   2 +
 .../powerpc64/multiarch/memcpy-power8-cached.S     | 179 +++++++++++++++++++++
 sysdeps/powerpc/powerpc64/multiarch/memcpy.c       |  23 +--
 12 files changed, 320 insertions(+), 13 deletions(-)
 create mode 100644 sysdeps/powerpc/cpu-features.c
 create mode 100644 sysdeps/powerpc/cpu-features.h
 create mode 100644 sysdeps/powerpc/dl-tunables.list
 create mode 100644 sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S

diff --git a/manual/tunables.texi b/manual/tunables.texi
index e851b95..17ceb64 100644
--- a/manual/tunables.texi
+++ b/manual/tunables.texi
@@ -319,6 +319,13 @@ the ones in @code{sysdeps/x86/cpu-features.h}.
 This tunable is specific to i386 and x86-64.
 @end deftp
 
+@deftp Tunable glibc.tune.cached_memopt
+The @code{glibc.tune.cached_memopt=[0|1]} tunable allows the user to enable
+optimizations recommended to cacheable memory.
+
+This tunable is specific to powerpc, powerpc64 and powerpc64le.
+@end deftp
+
 @deftp Tunable glibc.tune.cpu
 The @code{glibc.tune.cpu=xxx} tunable allows the user to tell @theglibc{} to
 assume that the CPU is @code{xxx} where xxx may have one of these values:
diff --git a/sysdeps/powerpc/cpu-features.c b/sysdeps/powerpc/cpu-features.c
new file mode 100644
index 0000000..6870582
--- /dev/null
+++ b/sysdeps/powerpc/cpu-features.c
@@ -0,0 +1,39 @@
+/* Initialize cpu feature data.  PowerPC version.
+   Copyright (C) 2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <stdint.h>
+#include <cpu-features.h>
+
+#if HAVE_TUNABLES
+# include <elf/dl-tunables.h>
+#endif
+
+static inline void
+init_cpu_features (struct cpu_features *cpu_features)
+{
+  /* Default is to use aligned memory access on optimized function unless
+     tunables is enable, since for this case user can explicit disable
+     unaligned optimizations.  */
+#if HAVE_TUNABLES
+  int32_t cached_memfunc = TUNABLE_GET (glibc, tune, cached_memopt, int32_t,
+					NULL);
+  cpu_features->use_cached_memopt = (cached_memfunc > 0);
+#else
+  cpu_features->use_cached_memopt = false;
+#endif
+}
diff --git a/sysdeps/powerpc/cpu-features.h b/sysdeps/powerpc/cpu-features.h
new file mode 100644
index 0000000..36a8bb4
--- /dev/null
+++ b/sysdeps/powerpc/cpu-features.h
@@ -0,0 +1,28 @@
+/* Initialize cpu feature data.  PowerPC version.
+   Copyright (C) 2017 Free Software Foundation, Inc.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef __CPU_FEATURES_POWERPC_H
+# define __CPU_FEATURES_POWERPC_H
+
+#include <stdbool.h>
+
+struct cpu_features
+{
+  bool use_cached_memopt;
+};
+
+#endif /* __CPU_FEATURES_H  */
diff --git a/sysdeps/powerpc/dl-procinfo.c b/sysdeps/powerpc/dl-procinfo.c
index 55a6e78..c8b14454d 100644
--- a/sysdeps/powerpc/dl-procinfo.c
+++ b/sysdeps/powerpc/dl-procinfo.c
@@ -42,6 +42,22 @@
 # define PROCINFO_CLASS
 #endif
 
+#if !IS_IN (ldconfig)
+# if !defined PROCINFO_DECL && defined SHARED
+  ._dl_powerpc_cpu_features
+# else
+PROCINFO_CLASS struct cpu_features _dl_powerpc_cpu_features
+# endif
+# ifndef PROCINFO_DECL
+= { }
+# endif
+# if !defined SHARED || defined PROCINFO_DECL
+;
+# else
+,
+# endif
+#endif
+
 #if !defined PROCINFO_DECL && defined SHARED
   ._dl_powerpc_cap_flags
 #else
diff --git a/sysdeps/powerpc/dl-tunables.list b/sysdeps/powerpc/dl-tunables.list
new file mode 100644
index 0000000..9e14b9a
--- /dev/null
+++ b/sysdeps/powerpc/dl-tunables.list
@@ -0,0 +1,28 @@
+# powerpc specific tunables.
+# Copyright (C) 2017 Free Software Foundation, Inc.
+# This file is part of the GNU C Library.
+
+# The GNU C Library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+
+# The GNU C Library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+
+# You should have received a copy of the GNU Lesser General Public
+# License along with the GNU C Library; if not, see
+# <http://www.gnu.org/licenses/>.
+
+glibc {
+  tune {
+    cached_memopt {
+      type: INT_32
+      minval: 0
+      maxval: 1
+      default: 0
+    }
+  }
+}
diff --git a/sysdeps/powerpc/ldsodefs.h b/sysdeps/powerpc/ldsodefs.h
index 466de79..6f8b3a2 100644
--- a/sysdeps/powerpc/ldsodefs.h
+++ b/sysdeps/powerpc/ldsodefs.h
@@ -20,6 +20,7 @@
 #define	_POWERPC_LDSODEFS_H	1
 
 #include <elf.h>
+#include <cpu-features.h>
 
 struct La_ppc32_regs;
 struct La_ppc32_retval;
diff --git a/sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h b/sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h
index f2e6a4b..6038941 100644
--- a/sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h
+++ b/sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h
@@ -37,6 +37,8 @@
 #define INIT_ARCH() \
   unsigned long int hwcap = __GLRO(dl_hwcap); 			\
   unsigned long int __attribute__((unused)) hwcap2 = __GLRO(dl_hwcap2); \
+  bool __attribute__((unused)) use_cached_memopt =		\
+    GLRO(dl_powerpc_cpu_features).use_cached_memopt;		\
   if (hwcap & PPC_FEATURE_ARCH_2_06)				\
     hwcap |= PPC_FEATURE_ARCH_2_05 |				\
 	     PPC_FEATURE_POWER5_PLUS |				\
diff --git a/sysdeps/powerpc/powerpc64/dl-machine.h b/sysdeps/powerpc/powerpc64/dl-machine.h
index aeb91b8..76dceee 100644
--- a/sysdeps/powerpc/powerpc64/dl-machine.h
+++ b/sysdeps/powerpc/powerpc64/dl-machine.h
@@ -27,6 +27,7 @@
 #include <dl-tls.h>
 #include <sysdep.h>
 #include <hwcapinfo.h>
+#include <cpu-features.c>
 
 /* Translate a processor specific dynamic tag to the index
    in l_info array.  */
@@ -300,13 +301,14 @@ BODY_PREFIX "_dl_start_user:\n"						\
 /* We define an initialization function to initialize HWCAP/HWCAP2 and
    platform data so it can be copied into the TCB later.  This is called
    very early in _dl_sysdep_start for dynamically linked binaries.  */
-#ifdef SHARED
+#if defined(SHARED) && IS_IN (rtld)
 # define DL_PLATFORM_INIT dl_platform_init ()
 
 static inline void __attribute__ ((unused))
 dl_platform_init (void)
 {
   __tcb_parse_hwcap_and_convert_at_platform ();
+  init_cpu_features (&GLRO(dl_powerpc_cpu_features));
 }
 #endif
 
diff --git a/sysdeps/powerpc/powerpc64/multiarch/Makefile b/sysdeps/powerpc/powerpc64/multiarch/Makefile
index dea49ac..4df6b45 100644
--- a/sysdeps/powerpc/powerpc64/multiarch/Makefile
+++ b/sysdeps/powerpc/powerpc64/multiarch/Makefile
@@ -1,6 +1,6 @@
 ifeq ($(subdir),string)
-sysdep_routines += memcpy-power7 memcpy-a2 memcpy-power6 memcpy-cell \
-		   memcpy-power4 memcpy-ppc64 \
+sysdep_routines += memcpy-power8-cached memcpy-power7 memcpy-a2 memcpy-power6 \
+		   memcpy-cell memcpy-power4 memcpy-ppc64 \
 		   memcmp-power8 memcmp-power7 memcmp-power4 memcmp-ppc64 \
 		   memset-power7 memset-power6 memset-power4 \
 		   memset-ppc64 memset-power8 \
diff --git a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
index 6a88536..77a60ea 100644
--- a/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
+++ b/sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
@@ -51,6 +51,8 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
 #ifdef SHARED
   /* Support sysdeps/powerpc/powerpc64/multiarch/memcpy.c.  */
   IFUNC_IMPL (i, name, memcpy,
+	      IFUNC_IMPL_ADD (array, i, memcpy, hwcap2 & PPC_FEATURE2_ARCH_2_07,
+			      __memcpy_power8_cached)
 	      IFUNC_IMPL_ADD (array, i, memcpy, hwcap & PPC_FEATURE_HAS_VSX,
 			      __memcpy_power7)
 	      IFUNC_IMPL_ADD (array, i, memcpy, hwcap & PPC_FEATURE_ARCH_2_06,
diff --git a/sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S b/sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S
new file mode 100644
index 0000000..e5b6f25
--- /dev/null
+++ b/sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S
@@ -0,0 +1,179 @@
+/* Optimized memcpy implementation for cached memory on PowerPC64/POWER8.
+   Copyright (C) 2017 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+
+
+/* __ptr_t [r3] memcpy (__ptr_t dst [r3], __ptr_t src [r4], size_t len [r5]);
+   Returns 'dst'.  */
+
+	.machine power8
+ENTRY_TOCLESS (__memcpy_power8_cached, 5)
+	CALL_MCOUNT 3
+
+	cmpldi	cr7,r5,15
+	bgt	cr7,L(ge_16)
+	andi.	r9,r5,0x1
+	mr	r9,r3
+	beq	cr0,1f
+	lbz	r10,0(r4)
+	addi	r9,r3,1
+	addi	r4,r4,1
+	stb	r10,0(r3)
+1:
+	andi.	r10,r5,0x2
+	beq	cr0,2f
+	lhz	r10,0(r4)
+	addi	r9,r9,2
+	addi	r4,r4,2
+	sth	r10,-2(r9)
+2:
+	andi.	r10,r5,0x4
+	beq	cr0,3f
+	lwz	r10,0(r4)
+	addi	r9,9,4
+	addi	r4,4,4
+	stw	r10,-4(r9)
+3:
+	andi.	r10,r5,0x8
+	beqlr	cr0
+	ld	r10,0(r4)
+	std	r10,0(r9)
+	blr
+
+	.align 4
+L(ge_16):
+	cmpldi	cr7,r5,32
+	ble	cr7,L(ge_16_le_32)
+	cmpldi	cr7,r5,64
+	ble	cr7,L(gt_32_le_64)
+
+	/* Align dst to 16 bytes.  */
+	andi.	r9,r3,0xf
+	mr	r12,r3
+	beq	cr0,L(dst_is_align_16)
+	lxvd2x	v0,r0,r4
+	subfic	r12,r9,16
+	subf	r5,r12,r5
+	add	r4,r4,r12
+	add	r12,r3,r12
+	stxvd2x	v0,r0,r3
+L(dst_is_align_16):
+	cmpldi	cr7,r5,127
+	ble	cr7,L(tail_copy)
+	addi	r8,r5,-128
+	mr	r9,r12
+	rldicr	r8,r8,0,56
+	li	r11,16
+	srdi	r10,r8,7
+	addi	r0,r8,128
+	addi	r10,r10,1
+	li	r6,32
+	mtctr	r10
+	li	r7,48
+
+	/* Main loop, copy 128 bytes each time.  */
+	.align 4
+L(copy_128):
+	lxvd2x	v10,r0,r4
+	lxvd2x	v11,r4,r11
+	addi	r8,r4,64
+	addi	r10,r9,64
+	lxvd2x	v12,r4,r6
+	lxvd2x	v0,r4,r7
+	addi	r4,r4,128
+	stxvd2x v10,r0,r9
+	stxvd2x v11,r9,r11
+	stxvd2x v12,r9,r6
+	stxvd2x v0,r9,r7
+	addi	r9,r9,128
+	lxvd2x	v10,r0,r8
+	lxvd2x	v11,r8,r11
+	lxvd2x	v12,r8,r6
+	lxvd2x	v0,r8,r7
+	stxvd2x v10,r0,r10
+	stxvd2x v11,r10,r11
+	stxvd2x v12,r10,r6
+	stxvd2x v0,r10,r7
+	bdnz	L(copy_128)
+
+	add	r12,r12,r0
+	rldicl 	r5,r5,0,57
+L(tail_copy):
+	cmpldi	cr7,r5,63
+	ble	cr7,L(tail_le_64)
+	li	r8,16
+	li	r10,32
+	lxvd2x	v10,r0,r4
+	li	r9,48
+	addi	r5,r5,-64
+	lxvd2x	v11,r4,r8
+	lxvd2x	v12,r4,r10
+	lxvd2x	v0,r4,r9
+	addi	r4,r4,64
+	stxvd2x	v10,r0,r12
+	stxvd2x	v11,r12,r8
+	stxvd2x	v12,r12,r10
+	stxvd2x	v0,r12,9
+	addi	r12,r12,64
+
+L(tail_le_64):
+	cmpldi	cr7,r5,32
+	bgt	cr7,L(tail_gt_32_le_64)
+	cmpdi	cr7,r5,0
+	beqlr	cr7
+	addi	r5,r5,-32
+	li	r9,16
+	add	r8,r4,r5
+	add	r10,r12,r5
+	lxvd2x	v12,r4,r5
+	lxvd2x	v0,r8,r9
+	stxvd2x	v12,r12,r5
+	stxvd2x	v0,r10,r9
+	blr
+
+	.align 4
+L(ge_16_le_32):
+	addi	r5,r5,-16
+	lxvd2x	v0,r0,r4
+	lxvd2x	v1,r4,r5
+	stxvd2x	v0,r0,r3
+	stxvd2x	v1,r3,r5
+	blr
+
+	.align 4
+L(gt_32_le_64):
+	mr	r12,r3
+
+	.align 4
+L(tail_gt_32_le_64):
+	li	r9,16
+	lxvd2x	v0,r0,r4
+	addi	r5,r5,-32
+	lxvd2x	v1,r4,r9
+	add	r8,r4,r5
+	lxvd2x	v2,r4,r5
+	add	r10,r12,r5
+	lxvd2x	v3,r8,r9
+	stxvd2x	v0,r0,r12
+	stxvd2x	v1,r12,r9
+	stxvd2x	v2,r12,r5
+	stxvd2x	v3,r10,r9
+	blr
+
+END_GEN_TB (__memcpy_power8_cached,TB_TOCLESS)
diff --git a/sysdeps/powerpc/powerpc64/multiarch/memcpy.c b/sysdeps/powerpc/powerpc64/multiarch/memcpy.c
index 9f4286c..fb49fe1 100644
--- a/sysdeps/powerpc/powerpc64/multiarch/memcpy.c
+++ b/sysdeps/powerpc/powerpc64/multiarch/memcpy.c
@@ -35,18 +35,21 @@ extern __typeof (__redirect_memcpy) __memcpy_cell attribute_hidden;
 extern __typeof (__redirect_memcpy) __memcpy_power6 attribute_hidden;
 extern __typeof (__redirect_memcpy) __memcpy_a2 attribute_hidden;
 extern __typeof (__redirect_memcpy) __memcpy_power7 attribute_hidden;
+extern __typeof (__redirect_memcpy) __memcpy_power8_cached attribute_hidden;
 
 libc_ifunc (__libc_memcpy,
-            (hwcap & PPC_FEATURE_HAS_VSX)
-            ? __memcpy_power7 :
-	      (hwcap & PPC_FEATURE_ARCH_2_06)
-	      ? __memcpy_a2 :
-		(hwcap & PPC_FEATURE_ARCH_2_05)
-		? __memcpy_power6 :
-		  (hwcap & PPC_FEATURE_CELL_BE)
-		  ? __memcpy_cell :
-		    (hwcap & PPC_FEATURE_POWER4)
-		    ? __memcpy_power4
+	    ((hwcap2 & PPC_FEATURE2_ARCH_2_07) && use_cached_memopt)
+	    ? __memcpy_power8_cached :
+	      (hwcap & PPC_FEATURE_HAS_VSX)
+	      ? __memcpy_power7 :
+		(hwcap & PPC_FEATURE_ARCH_2_06)
+		? __memcpy_a2 :
+		  (hwcap & PPC_FEATURE_ARCH_2_05)
+		  ? __memcpy_power6 :
+		    (hwcap & PPC_FEATURE_CELL_BE)
+		    ? __memcpy_cell :
+		      (hwcap & PPC_FEATURE_POWER4)
+		      ? __memcpy_power4
             : __memcpy_ppc);
 
 #undef memcpy
-- 
2.9.5

Re: [PATCHv2] powerpc: POWER8 memcpy optimization for cached memory

[Florian Weimer]

On 12/08/2017 08:40 PM, Tulio Magno Quites Machado Filho wrote:
> +@deftp Tunable glibc.tune.cached_memopt
> +The @code{glibc.tune.cached_memopt=[0|1]} tunable allows the user to enable
> +optimizations recommended to cacheable memory.
> +
> +This tunable is specific to powerpc, powerpc64 and powerpc64le.
> +@end deftp

I think this has a slight grammar problem.

What about this instead?

The @code{glibc.tune.cached_memopt=[0|1]} tunable allows the user to 
enable optimizations recommended for cacheable memory.  If set to 
@code{1}, @theglibc{} assumes that the process memory image consists of 
cacheable (non-device) memory only.  The default, @code{0}, indicates 
that the process may use device memory.

(I think it's best not to mention string functions here because it is 
impossible to describe how glibc.tune.cached_memopt affects them due to 
compiler optimizations.)

Thanks,
Florian

Re: [PATCHv2] powerpc: POWER8 memcpy optimization for cached memory

[Tulio Magno Quites Machado Filho]

Florian Weimer <fweimer@redhat.com> writes:

> On 12/08/2017 08:40 PM, Tulio Magno Quites Machado Filho wrote:
>> +@deftp Tunable glibc.tune.cached_memopt
>> +The @code{glibc.tune.cached_memopt=[0|1]} tunable allows the user to enable
>> +optimizations recommended to cacheable memory.
>> +
>> +This tunable is specific to powerpc, powerpc64 and powerpc64le.
>> +@end deftp
>
> I think this has a slight grammar problem.
>
> What about this instead?
>
> The @code{glibc.tune.cached_memopt=[0|1]} tunable allows the user to 
> enable optimizations recommended for cacheable memory.  If set to 
> @code{1}, @theglibc{} assumes that the process memory image consists of 
> cacheable (non-device) memory only.  The default, @code{0}, indicates 
> that the process may use device memory.

And a much better description.

> (I think it's best not to mention string functions here because it is 
> impossible to describe how glibc.tune.cached_memopt affects them due to 
> compiler optimizations.)

Ack.

Fixed locally.

Thanks!

-- 
Tulio Magno

Re: [PATCHv2] powerpc: POWER8 memcpy optimization for cached memory

[Adhemerval Zanella]

On 11/12/2017 10:44, Tulio Magno Quites Machado Filho wrote:
> Florian Weimer <fweimer@redhat.com> writes:
> 
>> On 12/08/2017 08:40 PM, Tulio Magno Quites Machado Filho wrote:
>>> +@deftp Tunable glibc.tune.cached_memopt
>>> +The @code{glibc.tune.cached_memopt=[0|1]} tunable allows the user to enable
>>> +optimizations recommended to cacheable memory.
>>> +
>>> +This tunable is specific to powerpc, powerpc64 and powerpc64le.
>>> +@end deftp
>>
>> I think this has a slight grammar problem.
>>
>> What about this instead?
>>
>> The @code{glibc.tune.cached_memopt=[0|1]} tunable allows the user to 
>> enable optimizations recommended for cacheable memory.  If set to 
>> @code{1}, @theglibc{} assumes that the process memory image consists of 
>> cacheable (non-device) memory only.  The default, @code{0}, indicates 
>> that the process may use device memory.
> 
> And a much better description.
> 
>> (I think it's best not to mention string functions here because it is 
>> impossible to describe how glibc.tune.cached_memopt affects them due to 
>> compiler optimizations.)
> 
> Ack.
> 
> Fixed locally.
> 
> Thanks!
> 

Thanks for working on this Tulio, LGTM.

Re: [PATCHv2] powerpc: POWER8 memcpy optimization for cached memory

[Rajalakshmi Srinivasaraghavan]

On 12/09/2017 01:10 AM, Tulio Magno Quites Machado Filho wrote:
> From: Adhemerval Zanella<azanella@linux.vnet.ibm.com>
> 
> I made the changes I requested, updated copyright entries, added a
> manual entry and fixed a build issue on powerpc64.
> 
> --- 8< ---
> 
> On POWER8, unaligned memory accesses to cached memory has little impact
> on performance as opposed to its ancestors.
> 
> It is disabled by default and will only be available when the tunable
> glibc.tune.cached_memopt is set to 1.
> 
>                   __memcpy_power8_cached      __memcpy_power7
> ============================================================
>      max-size=4096:     33325.70 ( 12.65%)        38153.00
>      max-size=8192:     32878.20 ( 11.17%)        37012.30
>     max-size=16384:     33782.20 ( 11.61%)        38219.20
>     max-size=32768:     33296.20 ( 11.30%)        37538.30
>     max-size=65536:     33765.60 ( 10.53%)        37738.40
> 
> 2017-12-08  Adhemerval Zanella<azanella@linux.vnet.ibm.com>
> 	    Tulio Magno Quites Machado Filho<tuliom@linux.vnet.ibm.com>
> 
> 	* manual/tunables.texi (Hardware Capability Tunables): Document
> 	glibc.tune.cached_memopt.
> 	* sysdeps/powerpc/cpu-features.c: New file.
> 	* sysdeps/powerpc/cpu-features.h: New file.
> 	* sysdeps/powerpc/dl-procinfo.c [!IS_IN(ldconfig)]: Add
> 	_dl_powerpc_cpu_features.
> 	* sysdeps/powerpc/dl-tunables.list: New file.
> 	* sysdeps/powerpc/ldsodefs.h: Include cpu-features.h.
> 	* sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h: .

Comment missing.
> 	* sysdeps/powerpc/powerpc64/dl-machine.h (INIT_ARCH): Initialize
> 	use_aligned_memopt.

Should this be moved to init-arch.h? (also use_cached_memopt)
> 	* sysdeps/powerpc/powerpc64/multiarch/Makefile (sysdep_routines):
> 	Add memcpy-power8-cached.
> 	* sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c: Add
> 	__memcpy_power8_cached.
> 	* sysdeps/powerpc/powerpc64/multiarch/memcpy.c: Likewise.
> 	* sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S:
> 	New file.
> ---
> diff --git a/sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S b/sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S
> new file mode 100644
> index 0000000..e5b6f25
> --- /dev/null
> +++ b/sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S
> @@ -0,0 +1,179 @@
> +	stxvd2x	v0,r0,r3
> +L(dst_is_align_16):
> +	cmpldi	cr7,r5,127
> +	ble	cr7,L(tail_copy)
> +	addi	r8,r5,-128
> +	mr	r9,r12
> +	rldicr	r8,r8,0,56
> +	li	r11,16
> +	srdi	r10,r8,7
> +	addi	r0,r8,128
> +	addi	r10,r10,1

Can we directly do
	rldicr  r0, r5, 0, 56
	srdi    r10,r5,7
instead of this sequence?
79         addi    r8,r5,-128
81         rldicr  r8,r8,0,56
83         srdi    r10,r8,7
84         addi    r0,r8,128
85         addi    r10,r10,1

> +	li	r6,32
> +	mtctr	r10
> +	li	r7,48
> +
> +	/* Main loop, copy 128 bytes each time.  */

LGTM.

Reviewed-by: Rajalakshmi Srinivasaraghavan  <raji@linux.vnet.ibm.com>


-- 
Thanks
Rajalakshmi S

Re: [PATCHv2] powerpc: POWER8 memcpy optimization for cached memory

[Tulio Magno Quites Machado Filho]

Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> writes:

> On 12/09/2017 01:10 AM, Tulio Magno Quites Machado Filho wrote:
>> 	* manual/tunables.texi (Hardware Capability Tunables): Document
>> 	glibc.tune.cached_memopt.
>> 	* sysdeps/powerpc/cpu-features.c: New file.
>> 	* sysdeps/powerpc/cpu-features.h: New file.
>> 	* sysdeps/powerpc/dl-procinfo.c [!IS_IN(ldconfig)]: Add
>> 	_dl_powerpc_cpu_features.
>> 	* sysdeps/powerpc/dl-tunables.list: New file.
>> 	* sysdeps/powerpc/ldsodefs.h: Include cpu-features.h.
>> 	* sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h: .
>
> Comment missing.

Ooops.

>> 	* sysdeps/powerpc/powerpc64/dl-machine.h (INIT_ARCH): Initialize
>> 	use_aligned_memopt.
>
> Should this be moved to init-arch.h? (also use_cached_memopt)

Indeed.
Changed to:

	* sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h
	(INIT_ARCH): Initialize use_aligned_memopt.
	* sysdeps/powerpc/powerpc64/dl-machine.h [defined(SHARED &&
	IS_IN(rtld))]: Restrict dl_platform_init availability and
	initialize CPU features used by tunables.

>> diff --git a/sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S b/sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S
>> new file mode 100644
>> index 0000000..e5b6f25
>> --- /dev/null
>> +++ b/sysdeps/powerpc/powerpc64/multiarch/memcpy-power8-cached.S
>> @@ -0,0 +1,179 @@
>> +	stxvd2x	v0,r0,r3
>> +L(dst_is_align_16):
>> +	cmpldi	cr7,r5,127
>> +	ble	cr7,L(tail_copy)
>> +	addi	r8,r5,-128
>> +	mr	r9,r12
>> +	rldicr	r8,r8,0,56
>> +	li	r11,16
>> +	srdi	r10,r8,7
>> +	addi	r0,r8,128
>> +	addi	r10,r10,1
>
> Can we directly do
> 	rldicr  r0, r5, 0, 56
> 	srdi    r10,r5,7
> instead of this sequence?
> 79         addi    r8,r5,-128
> 81         rldicr  r8,r8,0,56
> 83         srdi    r10,r8,7
> 84         addi    r0,r8,128
> 85         addi    r10,r10,1

Yes.  I changed that and made more changes for clarity:
 - Replaced rldicr with clrrdi.
 - Replace r0 with 0 where it's treated as an immediate.

Pushed as c9cd7b0ce5c5.

-- 
Tulio Magno

Re: [PATCH] powerpc: Use aligned stores in memset

[Andrew Pinski]

On Thu, Aug 17, 2017 at 10:11 PM, Rajalakshmi Srinivasaraghavan
<raji@linux.vnet.ibm.com> wrote:
> The powerpc hardware does not allow unaligned accesses on non cacheable
> memory.  This patch avoids misaligned stores for sizes less than 8 in
> memset to avoid such cases.  Tested on powerpc64 and powerpc64le.

Why are you using memset on non cacheable memory?  In fact how are you
getting non-cacheable memory, mmap of /dev/mem or something different?

Thanks,
Andrew

>
> 2017-08-17  Rajalakshmi Srinivasaraghavan  <raji@linux.vnet.ibm.com>
>
>         * sysdeps/powerpc/powerpc64/power8/memset.S: Store byte by byte
>         for unaligned inputs if size is less than 8.
> ---
>  sysdeps/powerpc/powerpc64/power8/memset.S | 68 ++++++++++++++++++++++++++++++-
>  1 file changed, 66 insertions(+), 2 deletions(-)
>
> diff --git a/sysdeps/powerpc/powerpc64/power8/memset.S b/sysdeps/powerpc/powerpc64/power8/memset.S
> index 7ad3bb1b00..504bab0841 100644
> --- a/sysdeps/powerpc/powerpc64/power8/memset.S
> +++ b/sysdeps/powerpc/powerpc64/power8/memset.S
> @@ -377,7 +377,8 @@ L(write_LT_32):
>         subf    r5,r0,r5
>
>  2:     bf      30,1f
> -       sth     r4,0(r10)
> +       stb     r4,0(r10)
> +       stb     r4,1(r10)
>         addi    r10,r10,2
>
>  1:     bf      31,L(end_4bytes_alignment)
> @@ -437,11 +438,74 @@ L(tail5):
>         /* Handles copies of 0~8 bytes.  */
>         .align  4
>  L(write_LE_8):
> -       bne     cr6,L(tail4)
> +       /* Use stb instead of sth which is safe for
> +          both aligned and unaligned inputs.  */
> +       bne     cr6,L(LE7_tail4)
> +       /* If input is word aligned, use stw, Else use stb.  */
> +       andi.   r0,r10,3
> +       bne     L(8_unalign)
>
>         stw     r4,0(r10)
>         stw     r4,4(r10)
>         blr
> +
> +       /* Unaligned input and size is 8.  */
> +       .align  4
> +L(8_unalign):
> +       andi.   r0,r10,1
> +       beq     L(8_hwalign)
> +       stb     r4,0(r10)
> +       sth     r4,1(r10)
> +       sth     r4,3(r10)
> +       sth     r4,5(r10)
> +       stb     r4,7(r10)
> +       blr
> +
> +       /* Halfword aligned input and size is 8.  */
> +       .align  4
> +L(8_hwalign):
> +       sth     r4,0(r10)
> +       sth     r4,2(r10)
> +       sth     r4,4(r10)
> +       sth     r4,6(r10)
> +       blr
> +
> +       .align  4
> +       /* Copies 4~7 bytes.  */
> +L(LE7_tail4):
> +       bf      29,L(LE7_tail2)
> +       stb     r4,0(r10)
> +       stb     r4,1(r10)
> +       stb     r4,2(r10)
> +       stb     r4,3(r10)
> +       bf      30,L(LE7_tail5)
> +       stb     r4,4(r10)
> +       stb     r4,5(r10)
> +       bflr    31
> +       stb     r4,6(r10)
> +       blr
> +
> +       .align  4
> +       /* Copies 2~3 bytes.  */
> +L(LE7_tail2):
> +       bf      30,1f
> +       stb     r4,0(r10)
> +       stb     r4,1(r10)
> +       bflr    31
> +       stb     r4,2(r10)
> +       blr
> +
> +       .align  4
> +L(LE7_tail5):
> +       bflr    31
> +       stb     r4,4(r10)
> +       blr
> +
> +       .align  4
> +1:     bflr    31
> +       stb     r4,0(r10)
> +       blr
> +
>  END_GEN_TB (MEMSET,TB_TOCLESS)
>  libc_hidden_builtin_def (memset)
>
> --
> 2.11.0
>

Re: [PATCH] powerpc: Use aligned stores in memset

[Tulio Magno Quites Machado Filho]

Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> writes:

> The powerpc hardware does not allow unaligned accesses on non cacheable
> memory.  This patch avoids misaligned stores for sizes less than 8 in
> memset to avoid such cases.  Tested on powerpc64 and powerpc64le.

This commit message is misleading.  I think it's necessary to improve with:

 1. Remove the first line.
 2. Mention the performance impact and what causes it.
 3. Reference the section "3.1.4.2 Alignment Interrupts" of the "POWER8
    Processor User's Manual for the Single-Chip Module", which describes
    this behavior.
 4. Mention which kind of programs are affected by the old behavior.

> 2017-08-17  Rajalakshmi Srinivasaraghavan  <raji@linux.vnet.ibm.com>
>
> 	* sysdeps/powerpc/powerpc64/power8/memset.S: Store byte by byte
> 	for unaligned inputs if size is less than 8.
> ---
>  sysdeps/powerpc/powerpc64/power8/memset.S | 68 ++++++++++++++++++++++++++++++-
>  1 file changed, 66 insertions(+), 2 deletions(-)
>
> diff --git a/sysdeps/powerpc/powerpc64/power8/memset.S b/sysdeps/powerpc/powerpc64/power8/memset.S
> index 7ad3bb1b00..504bab0841 100644
> --- a/sysdeps/powerpc/powerpc64/power8/memset.S
> +++ b/sysdeps/powerpc/powerpc64/power8/memset.S
> @@ -377,7 +377,8 @@ L(write_LT_32):
>  	subf	r5,r0,r5
>
>  2:	bf	30,1f
> -	sth	r4,0(r10)
> +	stb	r4,0(r10)
> +	stb	r4,1(r10)

Needs a comment to prevent future mistakes in the future.

> @@ -437,11 +438,74 @@ L(tail5):
>  	/* Handles copies of 0~8 bytes.  */
>  	.align	4
>  L(write_LE_8):
> -	bne	cr6,L(tail4)
> +	/* Use stb instead of sth which is safe for
> +	   both aligned and unaligned inputs.  */

I don't think "safe" is the correct term.  What about this?

    Use stb instead of sth because it doesn't generate alignment interrupts
    on cache-inhibited storage.

> +	bne	cr6,L(LE7_tail4)
> +	/* If input is word aligned, use stw, Else use stb.  */

s/Else/else/


-- 
Tulio Magno