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Tue, 30 Apr 2024 11:44:20 -0700 (PDT) Received: from [10.0.16.165] ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id v2-20020aa78082000000b006eab6ac1f83sm21498615pff.0.2024.04.30.11.44.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Apr 2024 11:44:20 -0700 (PDT) Message-ID: Date: Tue, 30 Apr 2024 11:44:16 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/7] RISC-V: Add Zbb optimized memchr as ifunc To: Palmer Dabbelt , adhemerval.zanella@linaro.org Cc: christoph.muellner@vrull.eu, libc-alpha@sourceware.org, Darius Rad , Andrew Waterman , philipp.tomsich@vrull.eu, Evan Green , DJ Delorie , kito.cheng@sifive.com, jeffreyalaw@gmail.com References: Content-Language: en-US From: Vineet Gupta In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 4/30/24 10:54, Palmer Dabbelt wrote: >>> That alone likely won't do it, there's a bunch of ordering rules in the ISA string handling so we might get tripped up on them.  We've got a fairly relaxed version of the rules in GCC to try and match the various older rules, though, so it might be possible to make something similar work. >>> >>> We should probably just add some sort of -march=+zbb type argument.  IIRC Kito was going to do it at some point, not sure if he got around to it? >> I am just pointing this out because I think the way RISCV extension selection >> is currently implemented makes it awkward to provide ifunc implementation in >> a agnostic way (specially now that RISCV has dozens of extensions) without >> knowing the current target compiler is generating. >> >> Some other ABI allows to either specify a ISA/chip reference (like powerpc >> with -mcpu=powerX) or a ABI extension directly (like aarch64 with -march=+xxx). > We have -mcpu, but for RISC-V that's even more fragmented than -march > (-mcpu essentially just rolls together -march and -mtune, and only > allows a curated list). The `-march=+`-type stuff has been a pretty > common request, I think someone just needst oget around to actually > implementing it. But the lack of this infra as of today, means downstream projects such as glibc either need to wait for that to get merged and rely on a specific gcc version or need to implement both ways of doing this. Unfortunately that means as of today we have to use the non perfect solutions. -Vineet