From: Mayshao-oc <Mayshao-oc@zhaoxin.com>
To: "H.J. Lu" <hjl.tools@gmail.com>
Cc: GNU C Library <libc-alpha@sourceware.org>,
Carlos O'Donell <carlos@redhat.com>,
"Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>,
"Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>,
"Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>,
"Ricky Li(BJ-RD)" <RickyLi@zhaoxin.com>
Subject: RE: [PATCH v2 1/3] x86: Add CPU Vendor ID detection support for Zhaoxin processors
Date: Fri, 10 Apr 2020 11:44:34 +0000 [thread overview]
Message-ID: <f1b4f4dd3c464613b8671ad015be585f@zhaoxin.com> (raw)
In-Reply-To: <CAMe9rOomk-kkvh7k=0XAy5ONt9fNscUMZGgzjr+SXTKdOSN45Q@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 3631 bytes --]
On Tue, Apr 7, 2020 at 8:38 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Sun, Mar 29, 2020 at 10:34 PM MayShao <MayShao@zhaoxin.com> wrote:
> >
> > To recognize Zhaoxin CPU Vendor ID, add a new architecture type
> > arch_kind_zhaoxin for Vendor Zhaoxin detection.
> >
> > ---
> > sysdeps/x86/cpu-features.c | 58
> ++++++++++++++++++++++++++++++++++++++++++++++
> > sysdeps/x86/cpu-features.h | 1 +
> > 2 files changed, 59 insertions(+)
> >
> > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> > index 81a170a..4d60553 100644
> > --- a/sysdeps/x86/cpu-features.c
> > +++ b/sysdeps/x86/cpu-features.c
> > @@ -466,6 +466,64 @@ init_cpu_features (struct cpu_features
> *cpu_features)
> > }
> > }
> > }
> > + /* This spells out "CentaurHauls" or " Shanghai ". */
> > + else if ((ebx == 0x746e6543 && ecx == 0x736c7561 && edx ==
> 0x48727561)
> > + || (ebx == 0x68532020 && ecx == 0x20206961 && edx ==
> 0x68676e61))
> > + {
> > + unsigned int extended_model, stepping;
> > +
> > + kind = arch_kind_zhaoxin;
> > +
> > + get_common_indices (cpu_features, &family, &model,
> &extended_model,
> > + &stepping);
> > +
> > + get_extended_indices (cpu_features);
> > +
> > +
>
> Single blank line.
>
> > + if (family == 0x6)
> > + {
> > + model += extended_model;
>
> Move it out of if block.
>
> > + if (model == 0xf || model == 0x19)
> > + {
> > + cpu_features->feature[index_arch_AVX_Usable]
> > + &= (~bit_arch_AVX_Usable
> > + & ~bit_arch_AVX2_Usable);
> > +
> > + cpu_features->feature[index_arch_Slow_SSE4_2]
> > + |= (bit_arch_Slow_SSE4_2);
> > +
> > +
> cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
> > + &= ~bit_arch_AVX_Fast_Unaligned_Load;
> > + }
> > + }
> > +
> > + if (family == 0x7)
>
> else if
>
> > + {
> > + model += extended_model;
>
> Remove it.
>
> > + if (model == 0x1b)
> > + {
> > + cpu_features->feature[index_arch_AVX_Usable]
> > + &= (~bit_arch_AVX_Usable
> > + & ~bit_arch_AVX2_Usable);
> > +
> > + cpu_features->feature[index_arch_Slow_SSE4_2]
> > + |= bit_arch_Slow_SSE4_2;
> > +
> > +
> cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
> > + &= ~bit_arch_AVX_Fast_Unaligned_Load;
> > + }
> > +
> > + if (model == 0x3b)
>
> else if
>
> > + {
> > + cpu_features->feature[index_arch_AVX_Usable]
> > + &= (~bit_arch_AVX_Usable
> > + & ~bit_arch_AVX2_Usable);
> > +
> > +
> cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
> > + &= ~bit_arch_AVX_Fast_Unaligned_Load;
> > + }
> > + }
> > + }
> > else
> > {
> > kind = arch_kind_other;
> > diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
> > index aea83e6..f05d5ce 100644
> > --- a/sysdeps/x86/cpu-features.h
> > +++ b/sysdeps/x86/cpu-features.h
> > @@ -53,6 +53,7 @@ enum cpu_features_kind
> > arch_kind_unknown = 0,
> > arch_kind_intel,
> > arch_kind_amd,
> > + arch_kind_zhaoxin,
> > arch_kind_other
> > };
> >
> > --
> > 2.7.4
> >
> >
Thank you for your comments, I have fixed the place you mentioned
and attached it to this email.
Best Regards,
May Shao
[-- Attachment #2: 0001-x86-Add-CPU-Vendor-ID-detection-support-for-Zhaoxin-.patch --]
[-- Type: application/octet-stream, Size: 2940 bytes --]
From 690346b59a7e5c915f5c0584f34badba735e9eee Mon Sep 17 00:00:00 2001
From: MayShao <mayshao-oc@zhaoxin.com>
Date: Fri, 10 Apr 2020 12:34:09 +0800
Subject: [PATCH v2 1/3] x86: Add CPU Vendor ID detection support for Zhaoxin
processors
To recognize Zhaoxin CPU Vendor ID, add a new architecture type
arch_kind_zhaoxin for Vendor Zhaoxin detection.
---
sysdeps/x86/cpu-features.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++
sysdeps/x86/cpu-features.h | 1 +
2 files changed, 55 insertions(+)
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 81a170a..bfb415f 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -466,6 +466,60 @@ init_cpu_features (struct cpu_features *cpu_features)
}
}
}
+ /* This spells out "CentaurHauls" or " Shanghai ". */
+ else if ((ebx == 0x746e6543 && ecx == 0x736c7561 && edx == 0x48727561)
+ || (ebx == 0x68532020 && ecx == 0x20206961 && edx == 0x68676e61))
+ {
+ unsigned int extended_model, stepping;
+
+ kind = arch_kind_zhaoxin;
+
+ get_common_indices (cpu_features, &family, &model, &extended_model,
+ &stepping);
+
+ get_extended_indices (cpu_features);
+
+ model += extended_model;
+ if (family == 0x6)
+ {
+ if (model == 0xf || model == 0x19)
+ {
+ cpu_features->feature[index_arch_AVX_Usable]
+ &= (~bit_arch_AVX_Usable
+ & ~bit_arch_AVX2_Usable);
+
+ cpu_features->feature[index_arch_Slow_SSE4_2]
+ |= (bit_arch_Slow_SSE4_2);
+
+ cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
+ &= ~bit_arch_AVX_Fast_Unaligned_Load;
+ }
+ }
+ else if (family == 0x7)
+ {
+ if (model == 0x1b)
+ {
+ cpu_features->feature[index_arch_AVX_Usable]
+ &= (~bit_arch_AVX_Usable
+ & ~bit_arch_AVX2_Usable);
+
+ cpu_features->feature[index_arch_Slow_SSE4_2]
+ |= bit_arch_Slow_SSE4_2;
+
+ cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
+ &= ~bit_arch_AVX_Fast_Unaligned_Load;
+ }
+ else if (model == 0x3b)
+ {
+ cpu_features->feature[index_arch_AVX_Usable]
+ &= (~bit_arch_AVX_Usable
+ & ~bit_arch_AVX2_Usable);
+
+ cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
+ &= ~bit_arch_AVX_Fast_Unaligned_Load;
+ }
+ }
+ }
else
{
kind = arch_kind_other;
diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
index aea83e6..f05d5ce 100644
--- a/sysdeps/x86/cpu-features.h
+++ b/sysdeps/x86/cpu-features.h
@@ -53,6 +53,7 @@ enum cpu_features_kind
arch_kind_unknown = 0,
arch_kind_intel,
arch_kind_amd,
+ arch_kind_zhaoxin,
arch_kind_other
};
--
2.7.4
next prev parent reply other threads:[~2020-04-10 11:44 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-30 5:33 [PATCH v2 0/3] x86: Add " MayShao
2020-03-30 5:33 ` [PATCH v2 1/3] x86: Add CPU Vendor ID detection " MayShao
2020-04-07 12:37 ` H.J. Lu
2020-04-10 11:44 ` Mayshao-oc [this message]
2020-03-30 5:33 ` [PATCH v2 2/3] x86: Add cache information " MayShao
2020-04-07 12:43 ` H.J. Lu
2020-04-10 2:34 ` Mayshao-oc
2020-04-10 11:53 ` H.J. Lu
2020-04-10 12:49 ` Mayshao-oc
2020-04-10 13:01 ` Mayshao-oc
2020-03-30 5:33 ` [PATCH v2 3/3] x86: Add the test case of __get_cpu_features " MayShao
2020-04-07 12:39 ` H.J. Lu
2020-04-08 2:36 ` May Shao(BJ-RD)
2020-04-08 12:52 ` Carlos O'Donell
[not found] ` <4b7ba83030284e9c9c5b1cd91f1b3012@zhaoxin.com>
2020-04-07 10:25 ` [PATCH v2 0/3] x86: Add " May Shao(BJ-RD)
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