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From: Adhemerval Zanella Netto <adhemerval.zanella@linaro.org>
To: "Andrew Pinski (QUIC)" <quic_apinski@quicinc.com>,
	Florian Weimer <fweimer@redhat.com>
Cc: "libc-alpha@sourceware.org" <libc-alpha@sourceware.org>
Subject: Re: [PATCH v2 2/2] Aarch64: Add new memset for Qualcomm's 0ryon-1 core
Date: Thu, 23 May 2024 10:08:07 -0300	[thread overview]
Message-ID: <f232ac12-ba2d-487b-a0b8-32220ec7463f@linaro.org> (raw)
In-Reply-To: <DM6PR02MB4058F21C72A27F9C0376DFB6B8EB2@DM6PR02MB4058.namprd02.prod.outlook.com>



On 22/05/24 20:01, Andrew Pinski (QUIC) wrote:
>> -----Original Message-----
>> From: Andrew Pinski (QUIC) <quic_apinski@quicinc.com>
>> Sent: Tuesday, May 14, 2024 12:41 AM
>> To: Florian Weimer <fweimer@redhat.com>; Andrew Pinski
>> (QUIC) <quic_apinski@quicinc.com>
>> Cc: libc-alpha@sourceware.org
>> Subject: RE: [PATCH v2 2/2] Aarch64: Add new memset for
>> Qualcomm's 0ryon-1 core
>>
>>> -----Original Message-----
>>> From: Florian Weimer <fweimer@redhat.com>
>>> Sent: Tuesday, May 14, 2024 12:32 AM
>>> To: Andrew Pinski (QUIC) <quic_apinski@quicinc.com>
>>> Cc: libc-alpha@sourceware.org
>>> Subject: Re: [PATCH v2 2/2] Aarch64: Add new memset for
>> Qualcomm's
>>> 0ryon-1 core
>>>
>>> * Andrew Pinski:
>>>
>>>> +L(try_zva):
>>>> +	/* Write the first and last 64 byte aligned block using
>> stp rather
>>>> +	   than using DC ZVA.  This is faster on some cores.
>>>> +	 */
>>>
>>> The “some cores” part seems outdated if it's just a memset
>> for the
>>> Oryon-1 core (singulare).  This comment and some others,
>> for example
>>
>> Will fix.
>>
>>>
>>>> +	/*
>>>> +	 * Adjust count and bias for loop. By subtracting extra 1
>> from count,
>>>> +	 * it is easy to use tbz instruction to check whether
>> loop tailing
>>>> +	 * count is less than 33 bytes, so as to bypass 2
>> unnecessary stps.
>>>> +	 */
>>>
>>> do not use GNU style.  This one is GNU style:
>>
>> This was copied exactly from memset_emag.S which has the
>> style issue in it too. It was in 9627ab99b50 commit where this
>> comment was introduced which copied from
>> memset_base64.S.
>> Should we fix the other files or just the new files? Because it
>> seems like having one version being based on the other once
>> and then changing the style in one case but not the other
>> seems wrong.
>> I suspect there many more GNU comment style issues in the
>> aarch64 mem* functions even.
> 
> Ping on this question? I don't want to update my patch until I get a further clarification on if the other files should be fixed in a similar way or if it is ok having the two files have different coding styles or should we just keep them the same.
> I don't care one way or the other, I will implement it either way. Though it seems like it should be up to the maintainer to fix up coding style issues of what was already there; it should not be the burden of person submitting code that is doing copying.

I see these specific coding styles as non-blocking issues, my expectation
would be to you fix it locally and install the patch.  If you want to fix
it on other files it would be good as well, but also not a requirement.

My understanding was that it was not caught back when EMAG implementation
were added.

  reply	other threads:[~2024-05-23 13:08 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-08 16:59 [PATCH v2 1/2] Aarch64: Add memcpy for qualcomm's oryon-1 core Andrew Pinski
2024-05-08 16:59 ` [PATCH v2 2/2] Aarch64: Add new memset for Qualcomm's 0ryon-1 core Andrew Pinski
2024-05-13 13:48   ` Florian Weimer
2024-05-14  6:19     ` Andrew Pinski (QUIC)
2024-05-14  7:37       ` Florian Weimer
2024-05-14  7:47         ` Andrew Pinski (QUIC)
2024-05-14  9:10           ` Florian Weimer
2024-05-14  7:32   ` Florian Weimer
2024-05-14  7:40     ` Andrew Pinski (QUIC)
2024-05-22 23:01       ` Andrew Pinski (QUIC)
2024-05-23 13:08         ` Adhemerval Zanella Netto [this message]
2024-05-14  7:35 ` [PATCH v2 1/2] Aarch64: Add memcpy for qualcomm's oryon-1 core Florian Weimer

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