From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id 24A3A385772D for ; Sat, 17 Feb 2024 03:53:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 24A3A385772D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 24A3A385772D Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708142033; cv=none; b=bw6yIE/wTj/FgydgF31xu8SvPwJIFQub1cC8cyNQg4VMirzKX14x4xy1d0IVQZmd4KAeou0pfG4RWTCfU+37HSa/kzoMqhPLE96Xr0IrhWLqxAAId+XGSYrwgEP9HqAOpPAY8OdEzA8sFhBUupGkHttl6Qhh6paPnnzjx9bckNc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708142033; c=relaxed/simple; bh=g+YM1B14EcUDbLXhv7p+P+6OV1ILbNyQP8WMkB/3K/Q=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=clTFUUGr6taXSxRqdSLAfKaHff73q6kOiXjsIDIT25Y8O1WF9dhwLXnjf2i7RXHhCEK1cpHVs2+b8Z7YOd6hm4Zgqx5fIzIUyTkBPwrdYF5v4i8K+vmGsGg3nTnWBNCd9/ylR76nRDaMMjPBMS0nrJz7TOVxmV78axA2CcrFvmU= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1708142030; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to; bh=X3w2ggvr8jPzW48Wr9p4j2PAT3qzbd75Ckl85H6fZ0w=; b=bJlZQXmi61b4zUZJoF/rgJzRxccWVgh9Ab68Lh/HE8TWazFIbReoFgK1lTiD/GKxkWzaVu 0dc/K20zMH8VqgPgnzKxAUQyrCT9Fldb78BKlqS9G5b/IclAzeaC8XG8RcTZdDRvCsx1qS yrUWOTbmmDcsK7fm5i6O/JEPMJ10GUE= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-30-TSoT0e-bM66S8Pk419WZJw-1; Fri, 16 Feb 2024 22:53:47 -0500 X-MC-Unique: TSoT0e-bM66S8Pk419WZJw-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 2C056101A52A; Sat, 17 Feb 2024 03:53:47 +0000 (UTC) Received: from greed.delorie.com (unknown [10.22.8.101]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 16619492BE2; Sat, 17 Feb 2024 03:53:47 +0000 (UTC) Received: from greed.delorie.com.redhat.com (localhost [127.0.0.1]) by greed.delorie.com (8.15.2/8.15.2) with ESMTP id 41H3rkwc324718; Fri, 16 Feb 2024 22:53:46 -0500 From: DJ Delorie To: Michael Jeanson Cc: libc-alpha@sourceware.org, mathieu.desnoyers@efficios.com, mjeanson@efficios.com Subject: Re: [PATCH v8 7/8] aarch64: Add rseq_load32_load32_relaxed In-Reply-To: <20240206162801.882585-8-mjeanson@efficios.com> Date: Fri, 16 Feb 2024 22:53:46 -0500 Message-ID: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Michael Jeanson writes: > This implementation is imported from the librseq project. Same comments as [6/8] wrt origin URL > diff --git a/sysdeps/unix/sysv/linux/aarch64/rseq-internal.h b/sysdeps/unix/sysv/linux/aarch64/rseq-internal.h > + Copyright (C) 2023 Free Software Foundation, Inc. Year? > +#define RSEQ_ASM_TMP_REG32 "w15" > +#define RSEQ_ASM_TMP_REG "x15" > +#define RSEQ_ASM_TMP_REG_2 "x14" > + > +#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \ > + post_commit_offset, abort_ip) \ > + " .pushsection __rseq_cs, \"aw\"\n" \ > + " .balign 32\n" \ > + __rseq_str(label) ":\n" \ > + " .long " __rseq_str(version) ", " __rseq_str(flags) "\n" \ > + " .quad " __rseq_str(start_ip) ", " \ > + __rseq_str(post_commit_offset) ", " \ > + __rseq_str(abort_ip) "\n" \ > + " .popsection\n\t" \ > + " .pushsection __rseq_cs_ptr_array, \"aw\"\n" \ > + " .quad " __rseq_str(label) "b\n" \ > + " .popsection\n" Ok. > +#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \ > + __RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \ > + (post_commit_ip - start_ip), abort_ip) Ok. > +/* > + * Exit points of a rseq critical section consist of all instructions outside > + * of the critical section where a critical section can either branch to or > + * reach through the normal course of its execution. The abort IP and the > + * post-commit IP are already part of the __rseq_cs section and should not be > + * explicitly defined as additional exit points. Knowing all exit points is > + * useful to assist debuggers stepping over the critical section. > + */ > +#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \ > + " .pushsection __rseq_exit_point_array, \"aw\"\n" \ > + " .quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n" \ > + " .popsection\n" Ok. > +#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \ > + " adrp " RSEQ_ASM_TMP_REG ", " __rseq_str(cs_label) "\n" \ > + " add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \ > + ", :lo12:" __rseq_str(cs_label) "\n" \ > + " str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(rseq_cs) "]\n" \ > + __rseq_str(label) ":\n" Ok. > +#define RSEQ_ASM_DEFINE_ABORT(label, abort_label) \ > + " b 222f\n" \ > + " .inst " __rseq_str(RSEQ_SIG_CODE) "\n" \ > + __rseq_str(label) ":\n" \ > + " b %l[" __rseq_str(abort_label) "]\n" \ > + "222:\n" Ok. > +#define RSEQ_ASM_OP_STORE(value, var) \ > + " str %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n" Ok. > +#define RSEQ_ASM_OP_STORE_RELEASE(value, var) \ > + " stlr %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n" Ok. > +#define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label) \ > + RSEQ_ASM_OP_STORE(value, var) \ > + __rseq_str(post_commit_label) ":\n" Ok. > +#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label) \ > + RSEQ_ASM_OP_STORE_RELEASE(value, var) \ > + __rseq_str(post_commit_label) ":\n" Ok. > +#define RSEQ_ASM_OP_CMPEQ(var, expect, label) \ > + " ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \ > + " sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \ > + ", %[" __rseq_str(expect) "]\n" \ > + " cbnz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n" This is why we need documentation; I would have guessed this was a CMPNE operation, but it depends on how you define "label" > +#define RSEQ_ASM_OP_CMPEQ32(var, expect, label) \ > + " ldr " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" \ > + " sub " RSEQ_ASM_TMP_REG32 ", " RSEQ_ASM_TMP_REG32 \ > + ", %w[" __rseq_str(expect) "]\n" \ > + " cbnz " RSEQ_ASM_TMP_REG32 ", " __rseq_str(label) "\n" Ok. > +#define RSEQ_ASM_OP_CMPNE(var, expect, label) \ > + " ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \ > + " sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \ > + ", %[" __rseq_str(expect) "]\n" \ > + " cbz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n" And of course this one is the opposite way ;-) > +#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \ > + RSEQ_ASM_OP_CMPEQ32(current_cpu_id, cpu_id, label) Ok. > +#define RSEQ_ASM_OP_R_LOAD(var) \ > + " ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" Ok. > +#define RSEQ_ASM_OP_R_STORE(var) \ > + " str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" Ok. > +#define RSEQ_ASM_OP_R_LOAD32(var) \ > + " ldr " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" Ok. > +#define RSEQ_ASM_OP_R_STORE32(var) \ > + " str " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" Ok. > +#define RSEQ_ASM_OP_R_LOAD_OFF(offset) \ > + " ldr " RSEQ_ASM_TMP_REG ", [" RSEQ_ASM_TMP_REG \ > + ", %[" __rseq_str(offset) "]]\n" Ok. > +#define RSEQ_ASM_OP_R_ADD(count) \ > + " add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \ > + ", %[" __rseq_str(count) "]\n" Ok. > +#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \ > + " str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \ > + __rseq_str(post_commit_label) ":\n" Ok. > +#define RSEQ_ASM_OP_R_FINAL_STORE32(var, post_commit_label) \ > + " str " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" \ > + __rseq_str(post_commit_label) ":\n" Ok. > +#define RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) \ > + " cbz %[" __rseq_str(len) "], 333f\n" \ > + " mov " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(len) "]\n" \ > + "222: sub " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", #1\n" \ > + " ldrb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(src) "]" \ > + ", " RSEQ_ASM_TMP_REG_2 "]\n" \ > + " strb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(dst) "]" \ > + ", " RSEQ_ASM_TMP_REG_2 "]\n" \ > + " cbnz " RSEQ_ASM_TMP_REG_2 ", 222b\n" \ > + "333:\n" Ok, but WHY? > +/* > + * Load @src1 (32-bit) into @dst1 and load @src2 (32-bit) into @dst2. > + */ > +#define RSEQ_HAS_LOAD32_LOAD32_RELAXED 1 > +static __always_inline int > +rseq_load32_load32_relaxed(uint32_t *dst1, uint32_t *src1, > + uint32_t *dst2, uint32_t *src2) > +{ > + __asm__ __volatile__ goto ( > + RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) > + RSEQ_ASM_STORE_RSEQ_CS(2, 1b, rseq_cs) > + RSEQ_ASM_OP_R_LOAD32(src1) > + RSEQ_ASM_OP_R_STORE32(dst1) > + RSEQ_ASM_OP_R_LOAD32(src2) > + RSEQ_ASM_OP_R_FINAL_STORE32(dst2, 3) > + RSEQ_ASM_DEFINE_ABORT(4, abort) > + : /* gcc asm goto does not allow outputs */ > + : [rseq_cs] "m" (rseq_get_area()->rseq_cs), > + [dst1] "Qo" (*dst1), > + [dst2] "Qo" (*dst2), > + [src1] "Qo" (*src1), > + [src2] "Qo" (*src2) > + : "memory", RSEQ_ASM_TMP_REG > + : abort > + ); > + rseq_after_asm_goto(); > + return 0; > +abort: > + rseq_after_asm_goto(); > + return -1; > +} Ok.