From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20101 invoked by alias); 30 Mar 2003 23:40:03 -0000 Mailing-List: contact libc-hacker-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-hacker-owner@sources.redhat.com Received: (qmail 20085 invoked from network); 30 Mar 2003 23:40:03 -0000 Received: from unknown (HELO gateway.sf.frob.com) (64.160.55.131) by sources.redhat.com with SMTP; 30 Mar 2003 23:40:03 -0000 Received: from magilla.sf.frob.com (magilla.sf.frob.com [198.49.250.228]) by gateway.sf.frob.com (Postfix) with ESMTP id 25E34354C; Sun, 30 Mar 2003 15:40:02 -0800 (PST) Received: (from roland@localhost) by magilla.sf.frob.com (8.11.6/8.11.6) id h2UNe1X00695; Sun, 30 Mar 2003 15:40:01 -0800 Date: Sun, 30 Mar 2003 23:59:00 -0000 Message-Id: <200303302340.h2UNe1X00695@magilla.sf.frob.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit From: Roland McGrath To: Jakub Jelinek Cc: Ulrich Drepper , Glibc hackers Subject: Re: [PATCH] sparc* bits/atomic.h In-Reply-To: Jakub Jelinek's message of Monday, 31 March 2003 00:44:05 +0200 <20030330224405.GA16629@sunsite.ms.mff.cuni.cz> X-Shopping-List: (1) Generic hootenanny contributions (2) Reverent lesions (3) Pyrotechnical clinical sandwich gumption X-SW-Source: 2003-03/txt/msg00144.txt.bz2 > 2003-03-31 Jakub Jelinek > > * sysdeps/sparc/sparc32/bits/atomic.h: New file. > * sysdeps/sparc/sparc32/sparcv9/bits/atomic.h: New file. > * sysdeps/sparc/sparc64/bits/atomic.h: New file. > > * sysdeps/sparc/sparc32/atomicity.h: Removed. > * sysdeps/sparc/sparc32/sparcv9/atomicity.h: Removed. > * sysdeps/sparc/sparc64/atomicity.h: Removed. Thanks, applied. > sparc32 (not v9) lacks compare and swap, so it is implemented using > test-and-set and a global lock. IMHO better than no locking at all, > performance will suck as usually on those aging boxes. Are there any actual MP boxes using those chips that Linux runs on? If not then you could use a software atomic sequence with kernel support like SH does. e.g., the low bit of the thread register says to reload the PC from some other register (and clear the flag bit). Thanks, Roland