2005-10-18 Steven Munroe * sysdeps/unix/sysv/linux/powerpc/powerpc32/ucontext_i.h (TESTS): Define. * sysdeps/unix/sysv/linux/powerpc/powerpc64/ucontext_i.h (UC_GPR0-UC_GPR31, UC_PC, UC_MSR, UC_CTR, UC_LR, UC_XER, UC_CCR, UC_FPR0, UC_FPR31, UC_FPCSR, TESTS): Define. diff -urN libc24-cvstip-20051017/sysdeps/unix/sysv/linux/powerpc/powerpc32/ucontext_i.h libc24/sysdeps/unix/sysv/linux/powerpc/powerpc32/ucontext_i.h --- libc24-cvstip-20051017/sysdeps/unix/sysv/linux/powerpc/powerpc32/ucontext_i.h 2004-01-15 22:49:35.000000000 -0600 +++ libc24/sysdeps/unix/sysv/linux/powerpc/powerpc32/ucontext_i.h 2005-10-18 15:31:08.142039136 -0500 @@ -41,3 +41,22 @@ #define _UC_VREGS 464 #define _UC_VSCR 976 #define _UC_VRSAVE 980 + +/* The registers don't have a fixed offset within ucontext because the + orginal ucontext only contained the regs pointer. Also with the + addition of VMX to the register state the mcontext may require + stronger alignment (16) then the containing ucontext (4). All access + to register state (pt_regs/mcontext) must be indirect via the regs + (uc_regs) pointer. This means we can't test the PPC32 register + offsets here. */ + +/* Tests run in stdlib/tst-ucontext-off. */ +#define TESTS \ + TEST (uc_link, _UC_LINK); \ + TEST (uc_stack.ss_sp, _UC_STACK_SP); \ + TEST (uc_stack.ss_size, _UC_STACK_SIZE); \ + TEST (uc_mcontext.regs, _UC_REGS_PTR); \ + TEST (uc_mcontext.uc_regs, _UC_REGS_PTR); \ + TEST (uc_sigmask, _UC_SIGMASK); \ + TEST (uc_reg_space, _UC_REG_SPACE); + diff -urN libc24-cvstip-20051017/sysdeps/unix/sysv/linux/powerpc/powerpc64/ucontext_i.h libc24/sysdeps/unix/sysv/linux/powerpc/powerpc64/ucontext_i.h --- libc24-cvstip-20051017/sysdeps/unix/sysv/linux/powerpc/powerpc64/ucontext_i.h 2004-01-15 22:49:59.000000000 -0600 +++ libc24/sysdeps/unix/sysv/linux/powerpc/powerpc64/ucontext_i.h 2005-10-18 14:37:38.085999376 -0500 @@ -58,3 +58,113 @@ #define SIGCONTEXT_FP_REGS 616 #define SIGCONTEXT_V_REGS_PTR 880 #define SIGCONTEXT_V_RESERVE 888 + +#define UC_GPR0 (SIGCONTEXT_GP_REGS + PT_R0 * 8) +#define UC_GPR1 (SIGCONTEXT_GP_REGS + PT_R1 * 8) +#define UC_GPR2 (SIGCONTEXT_GP_REGS + PT_R2 * 8) +#define UC_GPR3 (SIGCONTEXT_GP_REGS + PT_R3 * 8) +#define UC_GPR4 (SIGCONTEXT_GP_REGS + PT_R4 * 8) +#define UC_GPR5 (SIGCONTEXT_GP_REGS + PT_R5 * 8) +#define UC_GPR6 (SIGCONTEXT_GP_REGS + PT_R6 * 8) +#define UC_GPR7 (SIGCONTEXT_GP_REGS + PT_R7 * 8) +#define UC_GPR8 (SIGCONTEXT_GP_REGS + PT_R8 * 8) +#define UC_GPR9 (SIGCONTEXT_GP_REGS + PT_R9 * 8) +#define UC_GPR10 (SIGCONTEXT_GP_REGS + PT_R10 * 8) +#define UC_GPR11 (SIGCONTEXT_GP_REGS + PT_R11 * 8) +#define UC_GPR12 (SIGCONTEXT_GP_REGS + PT_R12 * 8) +#define UC_GPR13 (SIGCONTEXT_GP_REGS + PT_R13 * 8) +#define UC_GPR14 (SIGCONTEXT_GP_REGS + PT_R14 * 8) +#define UC_GPR15 (SIGCONTEXT_GP_REGS + PT_R15 * 8) +#define UC_GPR16 (SIGCONTEXT_GP_REGS + PT_R16 * 8) +#define UC_GPR17 (SIGCONTEXT_GP_REGS + PT_R17 * 8) +#define UC_GPR18 (SIGCONTEXT_GP_REGS + PT_R18 * 8) +#define UC_GPR19 (SIGCONTEXT_GP_REGS + PT_R19 * 8) +#define UC_GPR20 (SIGCONTEXT_GP_REGS + PT_R20 * 8) +#define UC_GPR21 (SIGCONTEXT_GP_REGS + PT_R21 * 8) +#define UC_GPR22 (SIGCONTEXT_GP_REGS + PT_R22 * 8) +#define UC_GPR23 (SIGCONTEXT_GP_REGS + PT_R23 * 8) +#define UC_GPR24 (SIGCONTEXT_GP_REGS + PT_R24 * 8) +#define UC_GPR25 (SIGCONTEXT_GP_REGS + PT_R25 * 8) +#define UC_GPR26 (SIGCONTEXT_GP_REGS + PT_R26 * 8) +#define UC_GPR27 (SIGCONTEXT_GP_REGS + PT_R27 * 8) +#define UC_GPR28 (SIGCONTEXT_GP_REGS + PT_R28 * 8) +#define UC_GPR29 (SIGCONTEXT_GP_REGS + PT_R29 * 8) +#define UC_GPR30 (SIGCONTEXT_GP_REGS + PT_R30 * 8) +#define UC_GPR31 (SIGCONTEXT_GP_REGS + PT_R31 * 8) + +#define UC_PC (SIGCONTEXT_GP_REGS + PT_NIP * 8) +#define UC_MSR (SIGCONTEXT_GP_REGS + PT_MSR * 8) +#define UC_CTR (SIGCONTEXT_GP_REGS + PT_CTR * 8) +#define UC_LR (SIGCONTEXT_GP_REGS + PT_LNK * 8) +#define UC_XER (SIGCONTEXT_GP_REGS + PT_XER * 8) +#define UC_CCR (SIGCONTEXT_GP_REGS + PT_CCR * 8) + +/* Since the FPRs are stored in a doubleword array there is nothing to + be gained by verifying individual FPRs. So verify FPR0 and FPR31 + to verify the compilers array indexing is correct. */ +#define UC_FPR0 (SIGCONTEXT_GP_REGS + PT_FPR0 * 8) +#define UC_FPR31 (SIGCONTEXT_GP_REGS + (PT_FPR0+31) * 8) +/* The FPSCR is stored as the 33rd entry in the fp_regs array. + PT_FPCSR is incorrect in asm/pthrace.h for older kernels. */ +#define UC_FPSCR (SIGCONTEXT_GP_REGS + (PT_FPR0+32) * 8) + +/* The VMX registers don't have a fixed offset within ucontext because + they requires stronger alignment (16) then the ucontext (8). All + accesses to VMX registers must be indirect via v_regs. This means + we can't test the VMX register offsets here. */ + +/* Tests run in stdlib/tst-ucontext-off. */ +#define TESTS \ + TEST (uc_link, UCONTEXT_LINK); \ + TEST (uc_stack.ss_sp, UCONTEXT_STACK_SP); \ + TEST (uc_stack.ss_size, UCONTEXT_STACK_SIZE); \ + TEST (uc_sigmask, UCONTEXT_SIGMASK); \ + TEST (uc_mcontext.signal, SIGCONTEXT_SIGNAL); \ + TEST (uc_mcontext.handler, SIGCONTEXT_HANDLER); \ + TEST (uc_mcontext.oldmask, SIGCONTEXT_OLDMASK); \ + TEST (uc_mcontext.regs, SIGCONTEXT_PT_REGS); \ + TEST (uc_mcontext.gp_regs, SIGCONTEXT_GP_REGS); \ + TEST (uc_mcontext.gp_regs[PT_R0], UC_GPR0); \ + TEST (uc_mcontext.gp_regs[PT_R1], UC_GPR1); \ + TEST (uc_mcontext.gp_regs[PT_R2], UC_GPR2); \ + TEST (uc_mcontext.gp_regs[PT_R3], UC_GPR3); \ + TEST (uc_mcontext.gp_regs[PT_R4], UC_GPR4); \ + TEST (uc_mcontext.gp_regs[PT_R5], UC_GPR5); \ + TEST (uc_mcontext.gp_regs[PT_R6], UC_GPR6); \ + TEST (uc_mcontext.gp_regs[PT_R7], UC_GPR7); \ + TEST (uc_mcontext.gp_regs[PT_R8], UC_GPR8); \ + TEST (uc_mcontext.gp_regs[PT_R9], UC_GPR9); \ + TEST (uc_mcontext.gp_regs[PT_R10], UC_GPR10); \ + TEST (uc_mcontext.gp_regs[PT_R11], UC_GPR11); \ + TEST (uc_mcontext.gp_regs[PT_R12], UC_GPR12); \ + TEST (uc_mcontext.gp_regs[PT_R13], UC_GPR13); \ + TEST (uc_mcontext.gp_regs[PT_R14], UC_GPR14); \ + TEST (uc_mcontext.gp_regs[PT_R15], UC_GPR15); \ + TEST (uc_mcontext.gp_regs[PT_R16], UC_GPR16); \ + TEST (uc_mcontext.gp_regs[PT_R17], UC_GPR17); \ + TEST (uc_mcontext.gp_regs[PT_R18], UC_GPR18); \ + TEST (uc_mcontext.gp_regs[PT_R19], UC_GPR19); \ + TEST (uc_mcontext.gp_regs[PT_R20], UC_GPR20); \ + TEST (uc_mcontext.gp_regs[PT_R21], UC_GPR21); \ + TEST (uc_mcontext.gp_regs[PT_R22], UC_GPR22); \ + TEST (uc_mcontext.gp_regs[PT_R23], UC_GPR23); \ + TEST (uc_mcontext.gp_regs[PT_R24], UC_GPR24); \ + TEST (uc_mcontext.gp_regs[PT_R25], UC_GPR25); \ + TEST (uc_mcontext.gp_regs[PT_R26], UC_GPR26); \ + TEST (uc_mcontext.gp_regs[PT_R27], UC_GPR27); \ + TEST (uc_mcontext.gp_regs[PT_R28], UC_GPR28); \ + TEST (uc_mcontext.gp_regs[PT_R29], UC_GPR29); \ + TEST (uc_mcontext.gp_regs[PT_R30], UC_GPR30); \ + TEST (uc_mcontext.gp_regs[PT_R31], UC_GPR31); \ + TEST (uc_mcontext.gp_regs[PT_NIP], UC_PC); \ + TEST (uc_mcontext.gp_regs[PT_MSR], UC_MSR); \ + TEST (uc_mcontext.gp_regs[PT_CTR], UC_CTR); \ + TEST (uc_mcontext.gp_regs[PT_LNK], UC_LR); \ + TEST (uc_mcontext.gp_regs[PT_XER], UC_XER); \ + TEST (uc_mcontext.gp_regs[PT_CCR], UC_CCR); \ + TEST (uc_mcontext.fp_regs, SIGCONTEXT_FP_REGS); \ + TEST (uc_mcontext.fp_regs[0], UC_FPR0); \ + TEST (uc_mcontext.fp_regs[31], UC_FPR31); \ + TEST (uc_mcontext.fp_regs[32], UC_FPSCR); \ + TEST (uc_mcontext.v_regs, SIGCONTEXT_V_REGS_PTR); \ + TEST (uc_mcontext.vmx_reserve, SIGCONTEXT_V_RESERVE);