From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 17178 invoked by alias); 15 Aug 2013 21:46:21 -0000 Mailing-List: contact libc-ports-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: libc-ports-owner@sourceware.org Received: (qmail 17168 invoked by uid 89); 15 Aug 2013 21:46:21 -0000 X-Spam-SWARE-Status: No, score=-6.2 required=5.0 tests=BAYES_00,KHOP_THREADED,RP_MATCHES_RCVD,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 Received: from hqemgate16.nvidia.com (HELO hqemgate16.nvidia.com) (216.228.121.65) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Thu, 15 Aug 2013 21:46:19 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 15 Aug 2013 14:46:15 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 15 Aug 2013 14:44:16 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 15 Aug 2013 14:44:16 -0700 Received: from HQMAIL02.nvidia.com ([172.20.150.110]) by hqemhub01.nvidia.com ([172.20.150.30]) with mapi; Thu, 15 Aug 2013 14:46:18 -0700 From: Abhishek Deb To: Dinar Temirbulatov , "libc-ports@sourceware.org" CC: "joseph@codesourcery.com" Date: Thu, 15 Aug 2013 21:46:00 -0000 Subject: RE: [Patch] ARM define atomic_exchange_acq/atomic_exchange_rel to __atomic_exchange_n Message-ID: <0E42B6C0C4628E48B8DF5D3F3C8FCA8898F1F8BF56@HQMAIL02.nvidia.com> References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-SW-Source: 2013-08/txt/msg00005.txt.bz2 Dinar, Apologies for delayed response, as I was on vacation. Your changes look in = line with the MIPS changes. Since GCC 4.7. onwards _atomic builtins are pro= vided, it's the right thing to do. I have not tested your changes, but I do= n't see anything obviously wrong.=20 Following is how the compiled code looks like, when compiled with gcc 4.8 Atomic_exchange_rel :=20 c8: f57ff05f dmb sy cc: e1952f9f ldrex r2, [r5] d0: e1851f93 strex r1, r3, [r5] d4: e3510000 cmp r1, #0 d8: 1afffffb bne cc=20 Atomic_exchange_acq : 94: e1953f9f ldrex r3, [r5] 98: e1852f97 strex r2, r7, [r5] 9c: e3520000 cmp r2, #0 a0: 1afffffb bne 94=20 a4: e3530000 cmp r3, #0 a8: 130f6c18 movwne r6, #64536 ; 0xfc18 ac: f57ff05f dmb sy So these changes look correct. However, taking a deeper look into atomic_compare_and_exchange_acq/rel, fol= lowing is how the compiled code looks like 34: f57ff05f dmb sy 38: e1903f9f ldrex r3, [r0] 3c: e3530000 cmp r3, #0 40: 1a000002 bne 50=20 44: e1801f92 strex r1, r2, [r0] 48: e3510000 cmp r1, #0 4c: 1afffff9 bne 38=20 50: e3530000 cmp r3, #0 54: f57ff05f dmb sy 58: 1afffff5 bne 34=20 As you can see it contains two memory barrier one in the beginning and one = in the end. Is it because gcc's _sync_* builtin was used? The _atomic_* bui= ltins provides users to specify memodel for each of the builtin functions. = Hence, shouldn't _atomic_ builtin with appropriate memmodel be used to do a= n atomic_compare_and_exchange_acq/rel? In other words for a acquire semantic the first dmb is redundant and for a = release semantic the second one is redundant. I don't know what do you thin= k. Abhishek -----Original Message----- From: Dinar Temirbulatov [mailto:dinar@kugelworks.com]=20 Sent: Tuesday, August 13, 2013 10:11 AM To: libc-ports@sourceware.org Cc: joseph@codesourcery.com; Abhishek Deb Subject: [Patch] ARM define atomic_exchange_acq/atomic_exchange_rel to __at= omic_exchange_n Hello, Following patch redefines atomic_exchange_acq/atomic_exchange_rel to __atom= ic_exchange_n for ARM, that allows for example to reduce number of instruct= ion sequence for lll_unlock from: ldex, cmp, bne, stex, cmp, bne to ldex, stex, cmp, bne , more on the issue here: http://sourceware.org/bugzilla/show_bug.cgi?id=3D15640 This patch was tested on ARM a9 with glibc testsuite with no new regression= s. OK to commit? Thanks, Dinar.