From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 17004 invoked by alias); 17 Aug 2013 02:42:17 -0000 Mailing-List: contact libc-ports-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: libc-ports-owner@sourceware.org Received: (qmail 16993 invoked by uid 89); 17 Aug 2013 02:42:17 -0000 X-Spam-SWARE-Status: No, score=-6.2 required=5.0 tests=AWL,BAYES_00,KHOP_THREADED,RP_MATCHES_RCVD,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 Received: from hqemgate14.nvidia.com (HELO hqemgate14.nvidia.com) (216.228.121.143) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Sat, 17 Aug 2013 02:42:16 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 16 Aug 2013 19:42:06 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 16 Aug 2013 19:42:14 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 16 Aug 2013 19:42:14 -0700 Received: from HQMAIL02.nvidia.com ([172.20.150.111]) by hqemhub03.nvidia.com ([172.20.150.15]) with mapi; Fri, 16 Aug 2013 19:42:14 -0700 From: Abhishek Deb To: Dinar Temirbulatov CC: "libc-ports@sourceware.org" , "joseph@codesourcery.com" Date: Sat, 17 Aug 2013 02:42:00 -0000 Subject: RE: [Patch] ARM define atomic_exchange_acq/atomic_exchange_rel to __atomic_exchange_n Message-ID: <0E42B6C0C4628E48B8DF5D3F3C8FCA8898F288A272@HQMAIL02.nvidia.com> References: <0E42B6C0C4628E48B8DF5D3F3C8FCA8898F1F8BF56@HQMAIL02.nvidia.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-SW-Source: 2013-08/txt/msg00008.txt.bz2 Dinar, As I said currently __arch_compare_and_exchange_val_32_acq is defined to __= sync_val_compare_and_swap ((mem), (oldval), (newval)), which probably uses = two dmb.=20 Can't __atomic_compare_exchange_n be used and appropriate memodel be specif= ied for acquire and release variants? -----Original Message----- From: Dinar Temirbulatov [mailto:dinar@kugelworks.com]=20 Sent: Friday, August 16, 2013 3:58 PM To: Abhishek Deb Cc: libc-ports@sourceware.org; joseph@codesourcery.com Subject: Re: [Patch] ARM define atomic_exchange_acq/atomic_exchange_rel to = __atomic_exchange_n Hello Abhishek, >However, taking a deeper look into atomic_compare_and_exchange_acq/rel, fo= llowing is how the compiled code looks like > > 34: f57ff05f dmb sy > 38: e1903f9f ldrex r3, [r0] > 3c: e3530000 cmp r3, #0 > 40: 1a000002 bne 50 > 44: e1801f92 strex r1, r2, [r0] > 48: e3510000 cmp r1, #0 > 4c: 1afffff9 bne 38 > 50: e3530000 cmp r3, #0 > 54: f57ff05f dmb sy > 58: 1afffff5 bne 34 oh, I see that lll_unlock looks correct on my side: .LBB12: .loc 1 42 0 dmb sy .L21: ldrex r2, [r4] strex r1, r3, [r4] cmp r1, #0 bne .L21 .LVL10: and for example __lll_cond_lock/__lll_timedlock also look right. But, I see that for lll_lock defined as : #define __lll_lock(futex, private) = \ ((void) ({ = \ int *__futex =3D (futex); = \ if (__builtin_expect (atomic_compare_and_exchange_val_acq (__futex, = \ 1, 0), 0)) = \ { = \ if (__builtin_constant_p (private) && (private) =3D=3D LLL_PRIVATE)= \ __lll_lock_wait_private (__futex); = \ else = \ __lll_lock_wait (__futex, private); = \ } = \ })) and we could see that on instruction level it looks like this: dmb sy .L91: ldrex r0, [r4] cmp r0, r3 bne .L92 strex r1, r7, [r4] cmp r1, #0 bne .L91 .L92: .LBE10: .loc 1 204 0 cmp r3, r0 .LBB11: .loc 1 202 0 dmb sy , so nothing wrong on my side. thanks, Dinar.