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From: Aurelien Jarno <aurelien@aurel32.net>
To: libc-ports@sourceware.org
Subject: [PATCH][alpha] Fix _SC_LEVEL*CACHE*
Date: Fri, 01 Apr 2011 21:19:00 -0000	[thread overview]
Message-ID: <20110401211854.GC16226@hall.aurel32.net> (raw)

sysconf() on alpha returns improper results for _SC_LEVEL*CACHE*
entries:

| LEVEL1_ICACHE_SIZE                 64
| LEVEL1_ICACHE_ASSOC                65536
| LEVEL1_ICACHE_LINESIZE             2
| LEVEL1_DCACHE_SIZE                 64
| LEVEL1_DCACHE_ASSOC                65536
| LEVEL1_DCACHE_LINESIZE             2
| LEVEL2_CACHE_SIZE                  64
| LEVEL2_CACHE_ASSOC                 4194304
| LEVEL2_CACHE_LINESIZE              1

This is due to the entries number being not properly aligned on modulo
3. This probably used to work at some point, but now that more entries
have been added, it doesn't work anymore. The patch below fixes that.


2011-04-01  Aurelien Jarno  <aurelien@aurel32.net>

        * sysdeps/unix/sysv/linux/alpha/sysconf.c: Fix cache sysconf
	switch.

diff --git a/sysdeps/unix/sysv/linux/alpha/sysconf.c b/sysdeps/unix/sysv/linux/alpha/sysconf.c
index 51a2a47..30faa3f 100644
--- a/sysdeps/unix/sysv/linux/alpha/sysconf.c
+++ b/sysdeps/unix/sysv/linux/alpha/sysconf.c
@@ -135,7 +135,7 @@ __sysconf (int name)
   if (shape <= 0)
     return shape;
 
-  switch (name % 3)
+  switch ((name - _SC_LEVEL1_ICACHE_SIZE) % 3)
     {
     case 0: /* total size */
       return shape & -0x100;
-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73aurelien@aurel32.net                 http://www.aurel32.net

             reply	other threads:[~2011-04-01 21:19 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-04-01 21:19 Aurelien Jarno [this message]
2012-02-19 12:51 ` Aurelien Jarno
2012-02-20 16:40   ` Richard Henderson

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