From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22143 invoked by alias); 11 Mar 2013 23:31:37 -0000 Received: (qmail 22132 invoked by uid 22791); 11 Mar 2013 23:31:36 -0000 X-SWARE-Spam-Status: No, hits=-2.1 required=5.0 tests=AWL,BAYES_00,TW_CB,TW_DR,TW_MV,TW_XF X-Spam-Check-By: sourceware.org Received: from toast.topped-with-meat.com (HELO topped-with-meat.com) (204.197.218.159) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 11 Mar 2013 23:31:23 +0000 Received: by topped-with-meat.com (Postfix, from userid 5281) id C2F1B2C083; Mon, 11 Mar 2013 16:31:20 -0700 (PDT) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit From: Roland McGrath To: Joseph Myers Cc: libc-ports@sourceware.org Subject: [PATCH roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb. Message-Id: <20130311233120.C2F1B2C083@topped-with-meat.com> Date: Mon, 11 Mar 2013 23:31:00 -0000 X-CMAE-Score: 0 X-CMAE-Analysis: v=2.1 cv=LYSvtFvi c=1 sm=1 tr=0 a=WkljmVdYkabdwxfqvArNOQ==:117 a=14OXPxybAAAA:8 a=vI0Rw-TFaOQA:10 a=Z6MIti7PxpgA:10 a=kj9zAlcOel0A:10 a=hOe2yjtxAAAA:8 a=Yq6XFD40IeMA:10 a=61MTDmXCat2PNc5riOAA:9 a=lEDen_N-bp4wlB2W:21 a=g21YiZxDp7JFL250:21 a=CjuIK1q_8ugA:10 X-IsSubscribed: yes Mailing-List: contact libc-ports-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: libc-ports-owner@sourceware.org X-SW-Source: 2013-03/txt/msg00102.txt.bz2 I have a target that is ARMv7-A but the OS does not permit any Thumb code. (My OS-specific sysdep.h will #define NO_THUMB.) This changes the memchr implementation to be usable without Thumb. Tested on armv7l-linux-gnueabihf: no test regressions, and the only changes in the code seen in disassembly are to the register allocation (what was r4,r5,r6 is now r6,r4,r5). I also tested the changes by locally hacking in #define NO_THUMB at the top of the file, and verified no test regressions with that build (and eyeball verified that it really did build the ARM-not-Thumb version of the code). OK? Thanks, Roland ports/ 2013-03-11 Roland McGrath * sysdeps/arm/armv6t2/memchr.S: Change register allocation so ldrd use is r4,r5 rather than r5,r6. [NO_THUMB]: Use .arm rather than .thumb, .thumb_func. Avoid cbz/cnbz instructions. --- a/ports/sysdeps/arm/armv6t2/memchr.S +++ b/ports/sysdeps/arm/armv6t2/memchr.S @@ -42,10 +42,12 @@ .syntax unified .text +#ifdef NO_THUMB + .arm +#else .thumb - -@ --------------------------------------------------------------------------- .thumb_func +#endif .global memchr .type memchr,%function ENTRY(memchr) @@ -83,20 +85,28 @@ ENTRY(memchr) orr r1, r1, r1, lsl #8 @ expand the match word across to all bytes orr r1, r1, r1, lsl #16 - bic r4, r2, #7 @ Number of double words to work with * 8 + bic r6, r2, #7 @ Number of double words to work with * 8 mvns r7, #0 @ all F's movs r3, #0 15: - ldrd r5,r6, [r0],#8 - subs r4, r4, #8 - eor r5,r5, r1 @ Get it so that r5,r6 have 00's where the bytes match the target - eor r6,r6, r1 + ldrd r4,r5, [r0],#8 +#ifndef NO_THUMB + subs r6, r6, #8 +#endif + eor r4,r4, r1 @ Get it so that r4,r5 have 00's where the bytes match the target + eor r5,r5, r1 + uadd8 r4, r4, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0 + sel r4, r3, r7 @ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION uadd8 r5, r5, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0 - sel r5, r3, r7 @ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION - uadd8 r6, r6, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0 - sel r6, r5, r7 @ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION - cbnz r6, 60f + sel r5, r4, r7 @ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION +#ifndef NO_THUMB + cbnz r5, 60f +#else + cmp r5, #0 + bne 60f + subs r6, r6, #8 +#endif bne 15b @ (Flags from the subs above) If not run out of bytes then go around again pop {r4,r5,r6,r7} @@ -110,13 +120,24 @@ ENTRY(memchr) and r2,r2,#7 @ Leave the count remaining as the number after the double words have been done 20: +#ifndef NO_THUMB cbz r2, 40f @ 0 length or hit the end already then not found +#else + cmp r2, #0 + beq 40f +#endif 21: @ Post aligned section, or just a short call ldrb r3,[r0],#1 +#ifndef NO_THUMB subs r2,r2,#1 eor r3,r3,r1 @ r3 = 0 if match - doesn't break flags from sub cbz r3, 50f +#else + eors r3, r3, r1 + beq 50f + subs r2, r2, #1 +#endif bne 21b @ on r2 flags 40: @@ -129,22 +150,22 @@ ENTRY(memchr) 60: @ We're here because the fast path found a hit - now we have to track down exactly which word it was @ r0 points to the start of the double word after the one that was tested - @ r5 has the 00/ff pattern for the first word, r6 has the chained value + @ r4 has the 00/ff pattern for the first word, r5 has the chained value cfi_restore_state - cmp r5, #0 + cmp r4, #0 itte eq - moveq r5, r6 @ the end is in the 2nd word + moveq r4, r5 @ the end is in the 2nd word subeq r0,r0,#3 @ Points to 2nd byte of 2nd word subne r0,r0,#7 @ or 2nd byte of 1st word @ r0 currently points to the 2nd byte of the word containing the hit - tst r5, # CHARTSTMASK(0) @ 1st character + tst r4, # CHARTSTMASK(0) @ 1st character bne 61f adds r0,r0,#1 - tst r5, # CHARTSTMASK(1) @ 2nd character + tst r4, # CHARTSTMASK(1) @ 2nd character ittt eq addeq r0,r0,#1 - tsteq r5, # (3<<15) @ 2nd & 3rd character + tsteq r4, # (3<<15) @ 2nd & 3rd character @ If not the 3rd must be the last one addeq r0,r0,#1