From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 30140 invoked by alias); 27 Jun 2012 22:04:31 -0000 Received: (qmail 30132 invoked by uid 22791); 27 Jun 2012 22:04:29 -0000 X-SWARE-Spam-Status: No, hits=-4.7 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_THREADED,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_WL X-Spam-Check-By: sourceware.org Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 27 Jun 2012 22:04:15 +0000 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1Sk0LO-0004r6-EJ from Maxim_Kuvyrkov@mentor.com ; Wed, 27 Jun 2012 15:04:14 -0700 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 27 Jun 2012 15:04:14 -0700 Received: from [127.0.0.1] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Wed, 27 Jun 2012 23:04:11 +0100 Subject: Re: [PATCH 1/3, MIPS] Rewrite MIPS' atomic.h to use __atomic_* builtins. MIME-Version: 1.0 (Apple Message framework v1278) Content-Type: text/plain; charset="us-ascii" From: Maxim Kuvyrkov In-Reply-To: Date: Wed, 27 Jun 2012 22:04:00 -0000 CC: , Richard Sandiford Content-Transfer-Encoding: quoted-printable Message-ID: <26D032BF-62BA-46CE-AD1B-05620E7D9A4C@codesourcery.com> References: <2D7F7056-72B4-455B-BD93-B216F5C5AFB6@codesourcery.com> To: Joseph S.Myers Mailing-List: contact libc-ports-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: libc-ports-owner@sourceware.org X-SW-Source: 2012-06/txt/msg00093.txt.bz2 On 15/06/2012, at 11:24 PM, Joseph S. Myers wrote: > On Fri, 15 Jun 2012, Maxim Kuvyrkov wrote: >=20 >> * sysdeps/mips/bit/atomic.h [__GNUC_PREREQ (4, 8)] >=20 > Again, "bits" not "bit". >=20 >> (__arch_compare_and_exchange_bool_acq_32_int,) >=20 > No comma before the closing parenthesis on each line. >=20 >> +#if __GNUC_PREREQ (4, 8) >> +/* The __atomic_* builtins are available in GCC 4.7 and later, but MIPS >> + support for their efficient implementation was added only in GCC 4.8= . */ >> + >> +/* Compare and exchange. >> + For all "bool" routines, we return FALSE if exchange succesful. */ >> + >> +#define __arch_compare_and_exchange_bool_acq_8_int(mem, newval, oldval)= \ >> + (abort (), 0) >=20 > "# define" inside #if (yes, this does mean adding spaces after the "#" fo= r=20 > the existing definitions that are now conditional). >=20 >> +/* This implementation using inline assembly will be removed once GLIBC >> + requires GCC 4.8 or later to build. */ >=20 > glibc, not GLIBC (see=20 > ). >=20 > More review later. Here is an updated patch fixed per above comments. -- Maxim Kuvyrkov CodeSourcery / Mentor Graphics Rewrite MIPS' atomic.h to use __atomic_* builtins. 2012-06-14 Tom de Vries Maxim Kuvyrkov * sysdeps/mips/bits/atomic.h [__GNUC_PREREQ (4, 8)] (__arch_compare_and_exchange_bool_acq_32_int) (__arch_compare_and_exchange_bool_rel_32_int) (__arch_compare_and_exchange_val_acq_32_int) (__arch_compare_and_exchange_val_rel_32_int) (__arch_compare_and_exchange_bool_acq_64_int) (__arch_compare_and_exchange_bool_rel_64_int) (__arch_compare_and_exchange_val_acq_64_int) (__arch_compare_and_exchange_val_rel_64_int): Define in terms of __atomic_compare_exchange_n. [__GNUC_PREREQ (4, 8)] (__arch_exchange_acq_32_int, __arch_exchange_rel_32_int) (__arch_exchange_acq_64_int, __arch_exchange_rel_64_int): Define in terms of __atomic_exchange_n. [__GNUC_PREREQ (4, 8)] (__arch_fetch_and_add_32_int, __arch_fetch_and_add_64_int): Define in terms of __atomic_fetch_add. [!__GNUC_PREREQ (4, 8)]: Update formatting. --- sysdeps/mips/bits/atomic.h | 257 +++++++++++++++++++++++++++++++++++++---= ---- 1 files changed, 217 insertions(+), 40 deletions(-) diff --git a/sysdeps/mips/bits/atomic.h b/sysdeps/mips/bits/atomic.h index 4d51d7f..9038624 100644 --- a/sysdeps/mips/bits/atomic.h +++ b/sysdeps/mips/bits/atomic.h @@ -1,5 +1,5 @@ /* Low-level functions for atomic operations. Mips version. - Copyright (C) 2005 Free Software Foundation, Inc. + Copyright (C) 2005-2012 Free Software Foundation, Inc. This file is part of the GNU C Library. =20 The GNU C Library is free software; you can redistribute it and/or @@ -78,17 +78,193 @@ typedef uintmax_t uatomic_max_t; #define MIPS_SYNC_STR_1(X) MIPS_SYNC_STR_2(X) #define MIPS_SYNC_STR MIPS_SYNC_STR_1(MIPS_SYNC) =20 +#if __GNUC_PREREQ (4, 8) +/* The __atomic_* builtins are available in GCC 4.7 and later, but MIPS + support for their efficient implementation was added only in GCC 4.8. = */ + +/* Compare and exchange. + For all "bool" routines, we return FALSE if exchange succesful. */ + +# define __arch_compare_and_exchange_bool_acq_8_int(mem, newval, oldval) \ + (abort (), 0) + +# define __arch_compare_and_exchange_bool_rel_8_int(mem, newval, oldval) \ + (abort (), 0) + +# define __arch_compare_and_exchange_bool_acq_16_int(mem, newval, oldval) \ + (abort (), 0) + +# define __arch_compare_and_exchange_bool_rel_16_int(mem, newval, oldval) \ + (abort (), 0) + +# define __arch_compare_and_exchange_bool_acq_32_int(mem, newval, oldval) \ + ({ \ + typeof (*mem) __oldval =3D (oldval); \ + !__atomic_compare_exchange_n (mem, &__oldval, newval, 0, \ + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); \ + }) + +# define __arch_compare_and_exchange_bool_rel_32_int(mem, newval, oldval) \ + ({ \ + typeof (*mem) __oldval =3D (oldval); \ + !__atomic_compare_exchange_n (mem, &__oldval, newval, 0, \ + __ATOMIC_RELEASE, __ATOMIC_RELAXED); \ + }) + +# define __arch_compare_and_exchange_val_acq_8_int(mem, newval, oldval) \ + (abort (), 0) + +# define __arch_compare_and_exchange_val_rel_8_int(mem, newval, oldval) \ + (abort (), 0) + +# define __arch_compare_and_exchange_val_acq_16_int(mem, newval, oldval) \ + (abort (), 0) + +# define __arch_compare_and_exchange_val_rel_16_int(mem, newval, oldval) \ + (abort (), 0) + +# define __arch_compare_and_exchange_val_acq_32_int(mem, newval, oldval) \ + ({ \ + typeof (*mem) __oldval =3D (oldval); \ + __atomic_compare_exchange_n (mem, &__oldval, newval, 0, \ + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); \ + __oldval; \ + }) + +# define __arch_compare_and_exchange_val_rel_32_int(mem, newval, oldval) \ + ({ \ + typeof (*mem) __oldval =3D (oldval); \ + __atomic_compare_exchange_n (mem, &__oldval, newval, 0, \ + __ATOMIC_RELEASE, __ATOMIC_RELAXED); \ + __oldval; \ + }) + +# if _MIPS_SIM =3D=3D _ABIO32 + /* We can't do an atomic 64-bit operation in O32. */ +# define __arch_compare_and_exchange_bool_acq_64_int(mem, newval, oldval)= \ + (abort (), 0) +# define __arch_compare_and_exchange_bool_rel_64_int(mem, newval, oldval)= \ + (abort (), 0) +# define __arch_compare_and_exchange_val_acq_64_int(mem, newval, oldval) \ + (abort (), 0) +# define __arch_compare_and_exchange_val_rel_64_int(mem, newval, oldval) \ + (abort (), 0) +# else +# define __arch_compare_and_exchange_bool_acq_64_int(mem, newval, oldval)= \ + __arch_compare_and_exchange_bool_acq_32_int (mem, newval, oldval) + +# define __arch_compare_and_exchange_bool_rel_64_int(mem, newval, oldval)= \ + __arch_compare_and_exchange_bool_rel_32_int (mem, newval, oldval) + +# define __arch_compare_and_exchange_val_acq_64_int(mem, newval, oldval) \ + __arch_compare_and_exchange_val_acq_32_int (mem, newval, oldval) + +# define __arch_compare_and_exchange_val_rel_64_int(mem, newval, oldval) \ + __arch_compare_and_exchange_val_rel_32_int (mem, newval, oldval) + +# endif + +/* Compare and exchange with "acquire" semantics, ie barrier after. */ + +# define atomic_compare_and_exchange_bool_acq(mem, new, old) \ + (__atomic_bool_bysize (__arch_compare_and_exchange_bool_acq, int, \ + mem, new, old)) + +# define atomic_compare_and_exchange_val_acq(mem, new, old) \ + __atomic_val_bysize (__arch_compare_and_exchange_val_acq, int, \ + mem, new, old) + +/* Compare and exchange with "release" semantics, ie barrier before. */ + +# define atomic_compare_and_exchange_bool_rel(mem, new, old) \ + (__atomic_bool_bysize (__arch_compare_and_exchange_bool_rel, int, \ + mem, new, old)) + +# define atomic_compare_and_exchange_val_rel(mem, new, old) \ + __atomic_val_bysize (__arch_compare_and_exchange_val_rel, int, \ + mem, new, old) + + +/* Atomic exchange (without compare). */ + +# define __arch_exchange_acq_8_int(mem, newval) \ + (abort (), 0) + +# define __arch_exchange_rel_8_int(mem, newval) \ + (abort (), 0) + +# define __arch_exchange_acq_16_int(mem, newval) \ + (abort (), 0) + +# define __arch_exchange_rel_16_int(mem, newval) \ + (abort (), 0) + +# define __arch_exchange_acq_32_int(mem, newval) \ + __atomic_exchange_n (mem, newval, __ATOMIC_ACQUIRE) + +# define __arch_exchange_rel_32_int(mem, newval) \ + __atomic_exchange_n (mem, newval, __ATOMIC_RELEASE) + +# if _MIPS_SIM =3D=3D _ABIO32 +/* We can't do an atomic 64-bit operation in O32. */ +# define __arch_exchange_acq_64_int(mem, newval) \ + (abort (), 0) +# define __arch_exchange_rel_64_int(mem, newval) \ + (abort (), 0) +# else +# define __arch_exchange_acq_64_int(mem, newval) \ + __atomic_exchange_n (mem, newval, __ATOMIC_ACQUIRE) + +# define __arch_exchange_rel_64_int(mem, newval) \ + __atomic_exchange_n (mem, newval, __ATOMIC_RELEASE) +# endif + +# define atomic_exchange_acq(mem, value) \ + __atomic_val_bysize (__arch_exchange_acq, int, mem, value) + +# define atomic_exchange_rel(mem, value) \ + __atomic_val_bysize (__arch_exchange_rel, int, mem, value) + + +/* Atomically add value and return the previous (unincremented) value. */ + +# define __arch_exchange_and_add_8_int(mem, newval) \ + (abort (), (typeof(*mem)) 0) + +# define __arch_exchange_and_add_16_int(mem, newval) \ + (abort (), (typeof(*mem)) 0) + +# define __arch_exchange_and_add_32_int(mem, value) \ + __atomic_fetch_add (mem, value, __ATOMIC_ACQ_REL) + +# if _MIPS_SIM =3D=3D _ABIO32 +/* We can't do an atomic 64-bit operation in O32. */ +# define __arch_exchange_and_add_64_int(mem, value) \ + (abort (), (typeof(*mem)) 0) +# else +# define __arch_exchange_and_add_64_int(mem, value) \ + __atomic_fetch_add (mem, value, __ATOMIC_ACQ_REL) +# endif + +/* ??? Barrier semantics for atomic_exchange_and_add appear to be + undefined. Use full barrier for now, as that's safe. */ +# define atomic_exchange_and_add(mem, value) \ + __atomic_val_bysize (__arch_exchange_and_add, int, mem, value) +#else /* !__GNUC_PREREQ (4, 8) */ +/* This implementation using inline assembly will be removed once glibc + requires GCC 4.8 or later to build. */ + /* Compare and exchange. For all of the "xxx" routines, we expect a "__prev" and a "__cmp" variable to be provided by the enclosing scope, in which values are returned. */ =20 -#define __arch_compare_and_exchange_xxx_8_int(mem, newval, oldval, rel, ac= q) \ +# define __arch_compare_and_exchange_xxx_8_int(mem, newval, oldval, rel, a= cq) \ (abort (), __prev =3D __cmp =3D 0) =20 -#define __arch_compare_and_exchange_xxx_16_int(mem, newval, oldval, rel, a= cq) \ +# define __arch_compare_and_exchange_xxx_16_int(mem, newval, oldval, rel, = acq) \ (abort (), __prev =3D __cmp =3D 0) =20 -#define __arch_compare_and_exchange_xxx_32_int(mem, newval, oldval, rel, a= cq) \ +# define __arch_compare_and_exchange_xxx_32_int(mem, newval, oldval, rel, = acq) \ __asm__ __volatile__ ( \ ".set push\n\t" \ MIPS_PUSH_MIPS2 \ @@ -107,12 +283,12 @@ typedef uintmax_t uatomic_max_t; : "r" (oldval), "r" (newval), "m" (*mem) \ : "memory") =20 -#if _MIPS_SIM =3D=3D _ABIO32 +# if _MIPS_SIM =3D=3D _ABIO32 /* We can't do an atomic 64-bit operation in O32. */ -#define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, a= cq) \ +# define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, = acq) \ (abort (), __prev =3D __cmp =3D 0) -#else -#define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, a= cq) \ +# else +# define __arch_compare_and_exchange_xxx_64_int(mem, newval, oldval, rel, = acq) \ __asm__ __volatile__ ("\n" \ ".set push\n\t" \ MIPS_PUSH_MIPS2 \ @@ -130,26 +306,26 @@ typedef uintmax_t uatomic_max_t; : "=3D&r" (__prev), "=3D&r" (__cmp), "=3Dm" (*mem) \ : "r" (oldval), "r" (newval), "m" (*mem) \ : "memory") -#endif +# endif =20 /* For all "bool" routines, we return FALSE if exchange succesful. */ =20 -#define __arch_compare_and_exchange_bool_8_int(mem, new, old, rel, acq) \ +# define __arch_compare_and_exchange_bool_8_int(mem, new, old, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \ !__cmp; }) =20 -#define __arch_compare_and_exchange_bool_16_int(mem, new, old, rel, acq) \ +# define __arch_compare_and_exchange_bool_16_int(mem, new, old, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \ !__cmp; }) =20 -#define __arch_compare_and_exchange_bool_32_int(mem, new, old, rel, acq) \ +# define __arch_compare_and_exchange_bool_32_int(mem, new, old, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \ !__cmp; }) =20 -#define __arch_compare_and_exchange_bool_64_int(mem, new, old, rel, acq) \ +# define __arch_compare_and_exchange_bool_64_int(mem, new, old, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \ !__cmp; }) @@ -157,43 +333,43 @@ typedef uintmax_t uatomic_max_t; /* For all "val" routines, return the old value whether exchange successful or not. */ =20 -#define __arch_compare_and_exchange_val_8_int(mem, new, old, rel, acq) \ +# define __arch_compare_and_exchange_val_8_int(mem, new, old, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __arch_compare_and_exchange_xxx_8_int(mem, new, old, rel, acq); \ (typeof (*mem))__prev; }) =20 -#define __arch_compare_and_exchange_val_16_int(mem, new, old, rel, acq) \ +# define __arch_compare_and_exchange_val_16_int(mem, new, old, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __arch_compare_and_exchange_xxx_16_int(mem, new, old, rel, acq); \ (typeof (*mem))__prev; }) =20 -#define __arch_compare_and_exchange_val_32_int(mem, new, old, rel, acq) \ +# define __arch_compare_and_exchange_val_32_int(mem, new, old, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __arch_compare_and_exchange_xxx_32_int(mem, new, old, rel, acq); \ (typeof (*mem))__prev; }) =20 -#define __arch_compare_and_exchange_val_64_int(mem, new, old, rel, acq) \ +# define __arch_compare_and_exchange_val_64_int(mem, new, old, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __arch_compare_and_exchange_xxx_64_int(mem, new, old, rel, acq); \ (typeof (*mem))__prev; }) =20 /* Compare and exchange with "acquire" semantics, ie barrier after. */ =20 -#define atomic_compare_and_exchange_bool_acq(mem, new, old) \ +# define atomic_compare_and_exchange_bool_acq(mem, new, old) \ __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \ mem, new, old, "", MIPS_SYNC_STR) =20 -#define atomic_compare_and_exchange_val_acq(mem, new, old) \ +# define atomic_compare_and_exchange_val_acq(mem, new, old) \ __atomic_val_bysize (__arch_compare_and_exchange_val, int, \ mem, new, old, "", MIPS_SYNC_STR) =20 /* Compare and exchange with "release" semantics, ie barrier before. */ =20 -#define atomic_compare_and_exchange_bool_rel(mem, new, old) \ +# define atomic_compare_and_exchange_bool_rel(mem, new, old) \ __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \ mem, new, old, MIPS_SYNC_STR, "") =20 -#define atomic_compare_and_exchange_val_rel(mem, new, old) \ +# define atomic_compare_and_exchange_val_rel(mem, new, old) \ __atomic_val_bysize (__arch_compare_and_exchange_val, int, \ mem, new, old, MIPS_SYNC_STR, "") =20 @@ -201,13 +377,13 @@ typedef uintmax_t uatomic_max_t; =20 /* Atomic exchange (without compare). */ =20 -#define __arch_exchange_xxx_8_int(mem, newval, rel, acq) \ +# define __arch_exchange_xxx_8_int(mem, newval, rel, acq) \ (abort (), 0) =20 -#define __arch_exchange_xxx_16_int(mem, newval, rel, acq) \ +# define __arch_exchange_xxx_16_int(mem, newval, rel, acq) \ (abort (), 0) =20 -#define __arch_exchange_xxx_32_int(mem, newval, rel, acq) \ +# define __arch_exchange_xxx_32_int(mem, newval, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __asm__ __volatile__ ("\n" \ ".set push\n\t" \ @@ -226,12 +402,12 @@ typedef uintmax_t uatomic_max_t; : "memory"); \ __prev; }) =20 -#if _MIPS_SIM =3D=3D _ABIO32 +# if _MIPS_SIM =3D=3D _ABIO32 /* We can't do an atomic 64-bit operation in O32. */ -#define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \ +# define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \ (abort (), 0) -#else -#define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \ +# else +# define __arch_exchange_xxx_64_int(mem, newval, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __asm__ __volatile__ ("\n" \ ".set push\n\t" \ @@ -249,24 +425,24 @@ typedef uintmax_t uatomic_max_t; : "r" (newval), "m" (*mem) \ : "memory"); \ __prev; }) -#endif +# endif =20 -#define atomic_exchange_acq(mem, value) \ +# define atomic_exchange_acq(mem, value) \ __atomic_val_bysize (__arch_exchange_xxx, int, mem, value, "", MIPS_SYNC= _STR) =20 -#define atomic_exchange_rel(mem, value) \ +# define atomic_exchange_rel(mem, value) \ __atomic_val_bysize (__arch_exchange_xxx, int, mem, value, MIPS_SYNC_STR= , "") =20 =20 /* Atomically add value and return the previous (unincremented) value. */ =20 -#define __arch_exchange_and_add_8_int(mem, newval, rel, acq) \ +# define __arch_exchange_and_add_8_int(mem, newval, rel, acq) \ (abort (), (typeof(*mem)) 0) =20 -#define __arch_exchange_and_add_16_int(mem, newval, rel, acq) \ +# define __arch_exchange_and_add_16_int(mem, newval, rel, acq) \ (abort (), (typeof(*mem)) 0) =20 -#define __arch_exchange_and_add_32_int(mem, value, rel, acq) \ +# define __arch_exchange_and_add_32_int(mem, value, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __asm__ __volatile__ ("\n" \ ".set push\n\t" \ @@ -285,12 +461,12 @@ typedef uintmax_t uatomic_max_t; : "memory"); \ __prev; }) =20 -#if _MIPS_SIM =3D=3D _ABIO32 +# if _MIPS_SIM =3D=3D _ABIO32 /* We can't do an atomic 64-bit operation in O32. */ -#define __arch_exchange_and_add_64_int(mem, value, rel, acq) \ +# define __arch_exchange_and_add_64_int(mem, value, rel, acq) \ (abort (), (typeof(*mem)) 0) -#else -#define __arch_exchange_and_add_64_int(mem, value, rel, acq) \ +# else +# define __arch_exchange_and_add_64_int(mem, value, rel, acq) \ ({ typeof (*mem) __prev; int __cmp; \ __asm__ __volatile__ ( \ ".set push\n\t" \ @@ -308,13 +484,14 @@ typedef uintmax_t uatomic_max_t; : "r" (value), "m" (*mem) \ : "memory"); \ __prev; }) -#endif +# endif =20 /* ??? Barrier semantics for atomic_exchange_and_add appear to be=20 undefined. Use full barrier for now, as that's safe. */ -#define atomic_exchange_and_add(mem, value) \ +# define atomic_exchange_and_add(mem, value) \ __atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \ MIPS_SYNC_STR, MIPS_SYNC_STR) +#endif /* __GNUC_PREREQ (4, 8) */ =20 /* TODO: More atomic operations could be implemented efficiently; only the basic requirements are done. */ --=20 1.7.4.1