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Date: Thu, 12 Dec 2013 22:19:00 -0000
Message-ID: <CA+=Sn1=87nKm1ShivDn5dJ29dNg5zYgQ58uSfWb18+mXh3-spA@mail.gmail.com>
Subject: Re: [patch, mips] Improved memset for MIPS
From: Andrew Pinski <pinskia@gmail.com>
To: Steve Ellcey <sellcey@mips.com>
Cc: "Joseph S. Myers" <joseph@codesourcery.com>, "Carlos O'Donell" <carlos@redhat.com>, 	"libc-ports@sourceware.org" <libc-ports@sourceware.org>
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On Fri, Sep 20, 2013 at 10:32 AM, Steve Ellcey <sellcey@mips.com> wrote:
> On Fri, 2013-09-20 at 16:43 +0000, Joseph S. Myers wrote:
>> On Wed, 18 Sep 2013, Steve Ellcey wrote:
>>
>> > 2013-09-18  Steve Ellcey  <sellcey@mips.com>
>> >
>> >     * sysdeps/mips/memset.S: Change prefetching and add loop unrolling.
>> >     * sysdeps/mips/mips64/memset.S: Remove.
>>
>> OK, though I believe "proAptive" in a comment should be "proAptiv".
>
> You are right.  I fixed that and checked in the patch.


I noticed this patch causes some performance regressions on Octeon due
to having 128 byte cache lines.
Changing PREFETCH_CHUNK/PREFETCH_FOR_STORE to assume 128 byte cache
line gives us the performance back and improves over the original code
at least 15%.
That is:
#  define PREFETCH_CHUNK 128
#  define PREFETCH_FOR_STORE(chunk, reg) \
    pref PREFETCH_STORE_HINT, (chunk)*128(reg);

Thanks,
Andrew Pinski

>
> Steve Ellcey
> sellcey@mips.com
>
>