From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18351 invoked by alias); 13 Dec 2013 00:22:59 -0000 Mailing-List: contact libc-ports-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: libc-ports-owner@sourceware.org Received: (qmail 18341 invoked by uid 89); 13 Dec 2013 00:22:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wg0-f51.google.com Received: from mail-wg0-f51.google.com (HELO mail-wg0-f51.google.com) (74.125.82.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 13 Dec 2013 00:22:58 +0000 Received: by mail-wg0-f51.google.com with SMTP id b13so1187288wgh.18 for ; Thu, 12 Dec 2013 16:22:55 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.180.7.136 with SMTP id j8mr510224wia.17.1386894175309; Thu, 12 Dec 2013 16:22:55 -0800 (PST) Received: by 10.217.90.70 with HTTP; Thu, 12 Dec 2013 16:22:55 -0800 (PST) In-Reply-To: <1386893669.2764.30.camel@ubuntu-sellcey> References: <93a232b5-9d0b-4a27-bbb5-16e3ae7c4b89@BAMAIL02.ba.imgtec.org> <1378483039.5770.302.camel@ubuntu-sellcey> <1378486241.5770.327.camel@ubuntu-sellcey> <1379526035.5770.414.camel@ubuntu-sellcey> <1379698355.5770.466.camel@ubuntu-sellcey> <1386893669.2764.30.camel@ubuntu-sellcey> Date: Fri, 13 Dec 2013 00:22:00 -0000 Message-ID: Subject: Re: [patch, mips] Improved memset for MIPS From: Andrew Pinski To: Steve Ellcey Cc: "Carlos O'Donell" , "Joseph S. Myers" , "Carlos O'Donell" , "libc-ports@sourceware.org" Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2013-12/txt/msg00015.txt.bz2 On Thu, Dec 12, 2013 at 4:14 PM, Steve Ellcey wrote: > On Thu, 2013-12-12 at 19:01 -0500, Carlos O'Donell wrote: > >> > I noticed this patch causes some performance regressions on Octeon due >> > to having 128 byte cache lines. >> > Changing PREFETCH_CHUNK/PREFETCH_FOR_STORE to assume 128 byte cache >> > line gives us the performance back and improves over the original code >> > at least 15%. >> > That is: >> > # define PREFETCH_CHUNK 128 >> > # define PREFETCH_FOR_STORE(chunk, reg) \ >> > pref PREFETCH_STORE_HINT, (chunk)*128(reg); >> >> Submit a patch for that? >> >> We have microbenchmarks now, but the next hardest >> part is going to be archiving data by device so that >> the community can help track performance and point >> out regressions like this. >> >> Cheers, >> Carlos. > > Unless the change is under some kind of ifdef for Octeon changing this > will probably slow down other MIPS chips. Most of them have 32 byte > cache lines. I think once ifunc support has been finalized, it would be useful to build memset optimized for Octeon but until then I think it might be best to disable the prefetching in the generic mips code. Thanks, Andrew Pinski > > Steve Ellcey > sellcey@mips.com > >