From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26558 invoked by alias); 21 Sep 2012 23:43:26 -0000 Received: (qmail 26550 invoked by uid 22791); 21 Sep 2012 23:43:25 -0000 X-SWARE-Spam-Status: No, hits=-4.8 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_THREADED,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_WL X-Spam-Check-By: sourceware.org Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 21 Sep 2012 23:43:12 +0000 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1TFCsJ-0000Y8-5T from joseph_myers@mentor.com ; Fri, 21 Sep 2012 16:43:11 -0700 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Fri, 21 Sep 2012 16:43:11 -0700 Received: from digraph.polyomino.org.uk (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Sat, 22 Sep 2012 00:43:08 +0100 Received: from jsm28 (helo=localhost) by digraph.polyomino.org.uk with local-esmtp (Exim 4.76) (envelope-from ) id 1TFCsF-0005kG-VK; Fri, 21 Sep 2012 23:43:07 +0000 Date: Fri, 21 Sep 2012 23:43:00 -0000 From: "Joseph S. Myers" To: Roland McGrath CC: Subject: Re: [PATCH roland/arm-atomic] ARM: split generic and Linux-specific bits/atomic.h In-Reply-To: <20120814235134.18B7B2C0EC@topped-with-meat.com> Message-ID: References: <20120814235134.18B7B2C0EC@topped-with-meat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Mailing-List: contact libc-ports-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: libc-ports-owner@sourceware.org X-SW-Source: 2012-09/txt/msg00068.txt.bz2 This patch caused around 150 test failures for pre-v6/v7 ARM systems using the kernel helpers, because the arguments in a call to __arm_assisted_compare_and_exchange_val_32_acq were the wrong way round. I've applied this patch to fix this. 2012-09-21 Joseph Myers * sysdeps/arm/bits/atomic.h [!__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4] (__arch_compare_and_exchange_val_32_acq): Correct order of arguments of __arm_assisted_compare_and_exchange_val_32_acq. diff --git a/ports/sysdeps/arm/bits/atomic.h b/ports/sysdeps/arm/bits/atomic.h index 9984210..39e276f 100644 --- a/ports/sysdeps/arm/bits/atomic.h +++ b/ports/sysdeps/arm/bits/atomic.h @@ -58,7 +58,7 @@ void __arm_link_error (void); __sync_val_compare_and_swap ((mem), (oldval), (newval)) #else # define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ - __arm_assisted_compare_and_exchange_val_32_acq ((mem), (oldval), (newval)) + __arm_assisted_compare_and_exchange_val_32_acq ((mem), (newval), (oldval)) #endif /* We don't support atomic operations on any non-word types. -- Joseph S. Myers joseph@codesourcery.com